Sony NW-A1000 Service Manual ▷ View online
NW-A1000
33
33
NW-A1000
Note: CN9201 cannot exchange with single. When CN9201
is damaged, exchange the entire mounted board.
5-13. SCHEMATIC DIAGRAM – MAIN Board (8/8) –
•
See page 23 for Waveforms.
•
See page 36 for IC Pin Function Description.
IC5001
R5005
C5011
C5010
FB5001
FB5002
C5015
C5016
FB5005
FB5006
C5018
C5012
C5013
R5011
R5012
R5014
R5016
C5020
C5025
R5003
C5003
C5005
C5006
C5007
C5008
C5004
R5004
FB5007
FB5008
R5017
R5018
R5019
R5020
C5027
C5026
C5024
C5019
R5008
R5009
C5009
R5007
R5015
R5013
R5010
C5022
C5021
R5048
R5054
R5047
C5029
C5023
C5014
C5017
CN5001
R5026
R5027
R5028
R5029
R5030
R5031
R5032
R5033
R5034
R5035
R5025
C5028
R5022
R5023
R5024
CN9201
R5036
R5037
R5038
R5039
R5040
R5041
R5042
R5043
R5044
R5045
FB5009
Q5001
R5006
X5001
FB5004
FB5003
R5052
C5002
R5001
R5002
R5051
FB5010
R5055
R5053
FB5011
TP9201
TP9204
TP9205
TP9206
R5050
R5049
TP9202
TP9203
CL5001
CL5002
CL5003
CL5004
CL5005
CL5006
CL5007
TP5001
R5021
TP9027
TP8077
TP8058
S1R72003B00A100
0
8p
8p
4.7
0.1
0.1
10p
100p
0
0
82
22
0.1
10
6.3V
5.6k
4.7
0.1
0.1
0.1
0.1
100p
100k
0
0
82
22
22
82
0.1
4.7
0.1
0.1
100k
100k
0.1
0
1M
47k
0
0.1
100
6.3V
0
0
0
0.01
0.1
0.1
0.1
39P
33
33
33
33
33
33
33
33
5.6k
10k
33
0.1
4.7k
10k
10k
42P
33
33
33
33
33
33
33
33
33
33
0
ECH8301-TL-E
1M
12MHz
0
0
0
1
10
100k
1K
0
0
0
0
0
0
10k
3.3V
GND
VBU
S
XREST_USB
XUSLEEP
FRES_A<23:1>
IDE_DIOR
IDE_DIOW
XINT_USB
FRES_D<31:16>
GND_HDD
3.3V_HDD
XHDD_PWR_CTL
D
CIN
D
C_
O
UT
JAC
K_D
ET
AD
P_
DET
AD
_C
RA
D
LE
CR
A
D
LE_SC
K
R
M
CKEY(K1)
CR
A
D
LE_
SO
CH
G
_LED
CR
A
D
LE_SI
CR
A
D
LE_CS
G
N
D
_A
IDE_IORDY
CR
D
_L
CR
D
_R
DAS
P
X
HC
S1
XH
CS
0
H
_A
2
H
_A
0
H
_A
1
H
IN
TR
Q
XH
DM
A
C
K
H_D0
H_D1
H_D2
H_D3
H_D4
H_D5
H_D6
H_D7
H_D8
H_D9
H_D10
H_D11
H_D12
H_D13
H_D14
H_D15
HDMARQ
XHIOW
XHIOR
XHIORDY
FRES_A1
FRES_A2
FRES_A3
FRES_A4
FRES_A5
FRES_A6
FRES_A7
FRES_A8
ID
E_D
IO
R
ID
E_D
IO
W
XINT_
US
B
FR
ES_D
24
FR
ES_D
25
FR
ES_D
26
FR
ES_D
27
FR
ES_D
28
FR
ES_D
29
FR
ES_D
30
FR
ES_D
31
IDE_DIOR
IDE_DIOW
XINT_USB
CRADLE_CS
CR
AD
L
E_CS
CRADLE_SI
C
RAD
LE_S
I
CHG_LED
CH
G
_LED
CRADLE_SO
C
RA
D
LE_S
O
RMCKEY(K1)
RM
C
KEY(K1)
CRADLE_SCK
C
RA
D
LE_S
CK
AD_CRADLE
AD_
CR
AD
LE
ADP_DET
AD
P_D
ET
CRD_R
CRD_L
JACK_DET
JAC
K_D
E
T
DC_OUT
DC_O
UT
DCIN
D
CIN
H_D10
H_D9
H_D2
H_D8
H_D1
H_D0
DASP
H_A0
XHDMACK
H_A1
HDMARQ
H_A2
XHIORDY
HINTRO
XHIOW
XHIOR
XHCS1
XHCS0
H_D15
H_D14
H_D13
H_D12
H_D11
PDIAG
H_D3
H_D4
H_D5
H_D6
H_D7
PD
IA
G
ID
E_IO
R
D
Y
IDE_IORDY
CRD
_L
C
RD
_
L
CA5
CA4
CA3
CA2
CA1
CA0
XSLEEP
XRESET
VBUS
TSTEN
AVDD
AVSS
DM
AVSS
DP
AVSS
AVDD
AVSS
AVDD
AVSS
N.C.
R1
CA7
CA6
VSS
VSS
OSCOUT
VSS
TIN1
TIN0
TPORT1
TPORT0
SCANEN
ATPGEN
VDD
CD7
CD6
CD5
CD4
VSS
CD3
CD2
CD1
CD0
XINT
XWR
XWAIT
XRD
XCS
VDD
VSS
HIORDY
XHIOR
XHIOW
HDMARQ
VDD
HDD15
HDD0
HDD14
HDD1
HDD13
HDD2
HDD12
HDD3
VSS
HDD11
HDD4
HDD10
HDD5
HDD9
HDD6
HDD8
HDD7
XHRESET
VDD
XO
XI
NC
NC
NC
PVSS
VDD
PVDD
VDD
XVDD
XVSS
VSS
CLKSEL1
CLKSEL0
VSS
XHDASP
XHCS1
XHCS0
HDA2
HDA0
XHPDIAG
HDA1
HINTRQ
XHDMACK
VDD
GND
GND
GND
CS
ID
SI
CHG_LED
SO
RM_KEY
SCLK
CRDL_MUTE1
DGND
CRDL_DET
ADP_DET
NC
NC
R
C_OUT
L
GND
AGND
GND
LINE_DET
GND
DIGIT_OUT
DC_OUT
DIGIT_IN
GND
5V
GND
5V
GND
VBUS
VBUS
GND
GND
D03
D11
D04
D12
D05
D13
D06
D14
D07
D15
CS0
CS1
IORW
INTRQ
VCC
VCC
VCC
RESET
IORDY
A02
A01
DMACK
A00
DASP
D00
PDIAG
D01
D08
D02
D09
D10
GND
GND
IORD(XHIOR)
VS2(OPEN)
DMARC(HDMARQ)
IOIS16(XIOCS16)
D
D
D
D
S
S
S
G
B+ SWITCH
USB CONTROLLER
∗
CSP(Chip Size Package)
AGND
GND
OR DOG SPEAKER
TO CHARGE CRADLE
VBUS
(8/8)
(6GB)
D+
D-
D-
D+
V_OUT/Y_OUT
(Page 29)
(Page 26)
(Page 26)
(Page 26)
(Page 32)
(Page 32)
(Page 32)
(Page 31)
(Page 29)
(Page 26)
NW-A1000
34
34
NW-A1000
•
IC Block Diagrams
IC3001
XC6219B302DR
IC3002
PCM1772RGAR
IC3003
AN17020A-VB
CE
6
NC
4
VSS
5
VIN 1
NC 2
VOUT 3
VCC
VCC
+
–
ON/OFF
CONTROL
CURRENT
LIMIT
VOLTAGE
REFERENCE
20
AUDIO
INTERFACE
DIGITAL
ATTENUATOR
LINEOUT
AMPLIFIER
LINEOUT
AMPLIFIER
LRCK
16
SCKI
17
NC
18
NC
19
NC
1
DATA
2
×
8
DIGITAL
FILTER
∆Σ
D/A
CONVERTER
∆Σ
D/A
CONVERTER
×
8
DIGITAL
FILTER
BCK
5
AGND2
4
AGND1
3
PD
7
VOUTR
6
VCOM
8
NC
9
VOUTR
10
AIN
15
SPI
PORT
MS
14 MC
CLOCK
MANAGER
DIGITAL
ATTENUATOR
13 MD
11 VCC2
12 VCC1
+
+
VCOM
POWER
SUPPLY
2
1
4
3
GND
CH1 IN
VCC 1HV
CH2 IN
15
16
13
14
+
−
MUTING
CTRL
CH1 SENS
BEEP
6
5
8
7
VCC1
RF
VCC2
VCC 2HV
BEEP
LINE AMP
HEADPHONE AMP
MUTING
+
−
LINE AMP
HEADPHONE AMP
12
11
9
10
CH1 OUT
PGND
CH2 SENS
CH2 OUT
REF1
VREF
REF2
HP/LINE
SWITCH
SWITCH
IC4101
R2061K01-E2
SIO 1
SCLK 2
7 OSCIN
VSB
4
VCC
5
VDD
6
CE
12
CIN
10
VSS
11
LEVEL
SHIFTER
DELAY
REAL
TIME
CLOCK
/VDCC 3
VOLTAGE
DETECTOR
BATTERY
VOLTAGE
VOLTAGE
MONITOR
8 OSCOUT
9 /INTR
VOLTAGE
REFERENCE
IC4202
HAAM-313B
1
DEMULTI-
PLEXER
MULTI-
PLEXER
GND
2
NC
4
NC
5
NC
3
STANDBY
10 ZOUT (A)
EEPROM
Z SENSOR
S/H
Y SENSOR
X SENSOR
9 YOUT (A)
S/H
AMPLIFIER
8 XOUT (A)
7 CSET
6 VCC
S/H
IC6003
TS5A3357DCUR
1
NO0
4
GND
7 COM
8 V+
LOGIC
CONTROL
2
NO1
3
NO2
5 IN2
6 IN1
35
NW-A1000
IC8301
TPS61045DRBR
8 SW
CTRL
5
PGND
6
GND
7
2
VIN
1
L
4
FB
3
DO
RS LATCH
LOGIC
UNDER VOLTAGE
LOCKOUT
BIAS SUPPLY
400 ns MIN
OFF TIME
6
µs MAX
ON TIME
GATE
DRIVER
GATE
DRIVER
DIGITAL
INTERFACE
6 BIT D/A
CONVERTER
S
R
+
–
+
–
ERROR COMPARATOR
VREF
CURRENT LIMIT
SOFT
START
CTRL
INPUT
SWITCH
MAIN
SWITCH
IC8302
TPS61041DBVR
1
SW
FB 3
GND 2
5 VIN
4 EN
RS LATCH
LOGIC
UNDER VOLTAGE
LOCKOUT
BIAS SUPPLY
400 ns MIN
OFF TIME
6
µs MAX
ON TIME
GATE
DRIVER
S
R
+
–
+
–
ERROR COMPARATOR
VREF
CURRENT LIMIT
SOFT
START
36
NW-A1000
•
IC Pin Function Description
IC3101 CXR710160-215GH (SUB SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
LRCK
I
L/R sampling clock signal input from the PLD
2
BCK
I
Bit clock signal input from the PLD
3
VDIOCD0
-
Power supply terminal (+1.8V) (for CD interface and I/O)
4
PCMD
I
Audio data input from the PLD
5
DVDD4
-
Power supply terminal (+1.3V)
6
TEST8
O
Output terminal for the test
7
TEST7
I
Input terminal for the test
8
DVDD0
-
Power supply terminal (+1.3V)
9
DVSS0
-
Ground terminal
10
VDIO0
-
Power supply terminal (+1.8V) (for I/O)
11
VDIOCD1
-
Power supply terminal (+1.8V) (for CD interface and I/O)
12
XRDE
I
Ready/busy selection signal input from the PLD "L": ready, "H": busy
13
BCK0
O
Bit clock signal output to the PLD
14
LRCK0
O
L/R sampling clock signal output to the PLD
15
PCMD0
O
Audio data output to the PLD
16
EVA
I
EVA mode selection signal input terminal
17
KCLK
O
Serial data transfer clock signal output terminal Not used
18
KCS
O
Chip select signal output terminal Not used
19
VDIO01
-
Power supply terminal (+1.8V) (for I/O)
20
KDO
O
Serial data output terminal Not used
21
KDI
I
Serial data input terminal Not used
22
KRB
O
Ready/busy selection signal output terminal Not used
23
DVDD1
-
Power supply terminal (+1.3V)
24
DVSS3
-
Ground terminal
25
AVDPLL
-
Power supply terminal (+3V) (for PLL)
26
AVSPLL
-
Ground terminal (for PLL)
27
AVSOSC
-
Ground terminal (for OSC)
28
AVDMO
-
Power supply terminal (+3V) (for OSC)
29
EXTAL
I
Main system clock input terminal (22.5792 MHz)
30
XTAL
O
Main system clock output terminal (22.5792 MHz)
31
XIN
I
External clock input terminal Not used
32
OSSEL
I
External clock control signal input terminal Not used
33
NRST
I
Reset signal input from the PLD "L": reset
34
PF0
I
Wake-up signal input from the PLD
35
PF1
O
Ready signal output to the PLD
36
PF2
I
Interrupt request signal input from the PLD
37
PF3
O
Interrupt request signal output to the PLD
38
PC0
I
Serial data transfer clock signal input from the PLD
39
VDIOCD2
-
Power supply terminal (+1.8V) (for CD interface and I/O)
40
PC1
O
Serial data output to the PLD
41
PC2
I
Serial data input from the PLD
42
PC3
O
Chip select signal output to the PLD
43
DVDD2
-
Power supply terminal (+1.3V)
44
DVSS2
-
Ground terminal
45 to 48
PE0 to PE3
I/O
Not used
49
VDIO2
-
Power supply terminal (+1.8V) (for I/O)
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