Sony NAS-S55HDE / NAS-SC55PKE / SS-S55HDE Service Manual ▷ View online
NAS-S55HDE/SS-S55HDE
73
Pin No.
Pin Name
I/O
Description
81, 82
AD1, AD0
I/O
Address signal and data input/output with the ethernet interface, CPU and audio DSP inter-
face
face
83
CRNU0
I/O
Not used
84, 85
NC
-
Not used
86
SMI0
O
Not used
87
AMC
I
Not used
88
TEB
I
Not used
89
SMC
I
Not used
90
LEGC
I
Legacy support switch input terminal
"L": Legacy off, "H": Legacy on Fixed at "L" in this set
"L": Legacy off, "H": Legacy on Fixed at "L" in this set
91
TEST
I
Not used
92
NTEST1
I
Not used
93
VDD
-
Power supply terminal (+3.3V)
94
XT2
O
Not used
95
XT1/SCLK
I
Clock signal (48 MHz) input from the clock generator
96
SRCLK
O
Not used
97
SRMOD
I
Not used
98
SRDTA
I/O
Not used
99
NANDTEST
I
Not used
100, 101
VSS
-
Ground terminal
102
AVDD
-
Power supply terminal (+3.3V)
103
RREF
-
Not used
104
AVSSR
-
Ground terminal
105
AVSS
-
Ground terminal
106
AVDD
-
Power supply terminal (+3.3V)
107
AVSS
-
Ground terminal
108
VDD
-
Power supply terminal (+3.3V)
109, 110
VSS
-
Ground terminal
111
RSDM1
O
USB D- full speed signal output terminal
112
DM1
I/O
USB D- high speed signal input/output with the USB connector
113
VDD
-
Power supply terminal (+3.3V)
114
DP1
I/O
USB D+ high speed signal input/output with the USB connector
115
RSDP1
O
USB D+ full speed signal output terminal
116
VSS
-
Ground terminal
117
RSDM2
O
Not used
118
DM2
I/O
Not used
119
VDD
-
Power supply terminal (+3.3V)
120
DP2
I/O
Not used
121
RSDP2
O
Not used
122, 123
VSS
-
Ground terminal
124
VDD
-
Power supply terminal (+3.3V)
125
VSS
-
Ground terminal
126
RSDM3
O
Not used
127
DM3
I/O
Not used
128
VDD
-
Power supply terminal (+3.3V)
129
DP3
I/O
Not used
130
RSDP3
O
Not used
131
VSS
-
Ground terminal
132
RSDM4
O
USB D- full speed signal output terminal
133
DM4
I/O
USB D- high speed signal input/output with the USB connector
134
VDD
-
Power supply terminal (+3.3V)
135
DP4
I/O
USB D+ high speed signal input/output with the USB connector
136
RSDP4
O
USB D+ full speed signal output terminal
137
VSS
-
Ground terminal
138
RSDM5
O
Not used
139
DM5
I/O
Not used
140
VDD
-
Power supply terminal (+3.3V)
141
DP5
I/O
Not used
142
RSDP5
O
Not used
143, 144
VSS
-
Ground terminal
NAS-S55HDE/SS-S55HDE
74
MOTHER BOARD IC5001 88SA8040C0-TBC1C000 (HDD DRIVER)
Pin No.
Pin Name
I/O
Description
1 to 3
H_DD13, H_DD2,
H_DD12
I/O
Two-way data bus with the CPU
4
VDDIO
-
Power supply terminal (+3.3V) (for digital I/O)
5 to 7
H_DD3, H_DD11,
H_DD4
I/O
Two-way data bus with the CPU
8
GND
-
Ground terminal (digital system)
9
VDD
-
Power supply terminal (+1.8V) (for digital logic)
10 to15
H_DD10, H_DD5,
H_DD9, H_DD6,
H_DD8, H_DD7
I/O
Two-way data bus with the CPU
16
H_RESET_N
I
Reset signal input from the CPU
17
RST_N
I
Reset signal input from the CPU "L": reset
18 to 20
CNFG0 to CFNG2
I
Confi guration terminal
21
ATAIOSEL
I
ATA I/O on/off enable signal input terminal Not used
22
XTLIN/OSC
I
System clock input terminal (25 MHz)
23
XTLOUT
O
System clock output terminal (25 MHz)
24
VAA1
-
Power supply terminal (+3.3V) (for TBG analog)
25
VSS1
-
Ground terminal (analog system)
26
ISET
O
Bias current output terminal
27, 28
RX_P, RX_M
I
Receive data input from the hard disk drive
29
VAA2
-
Power supply terminal (+3.3V) (for PHY analog)
30
VSS2
-
Ground terminal (analog system)
31, 32
TX_M, TX_P
O
Transmit data output to the hard disk drive
33 to 40
T0 to T7
I
Not used
41
VDD
-
Power supply terminal (+1.8V) (for digital logic)
42
GND
-
Ground terminal (digital system)
43
UAI
I
Not used
44
VDDIO
-
Power supply terminal (+3.3V) (for digital I/O)
45
UAO
O
Not used
46
H_PDIAG_N
I
PATA order mode setting signal input terminal
"L": normal order mode, "H": reverse order mode Fixed at "L" in this set
"L": normal order mode, "H": reverse order mode Fixed at "L" in this set
47, 48
H_CS_N1, H_CS_N0
I
Chip select signal input from the CPU
49 to 51
H_DA2, H_DA0,
H_DA1
I
Address signal input from the CPU
52
H_IOCS16_N
O
Not used
53
H_INTRQ
O
Interrupt signal output to the CPU
54
H_DMACK_N
I
Clock signal input from the CPU
55
H_IORDY
O
Ready signal output to the CPU
56
VDD
-
Power supply terminal (+1.8V) (for digital logic)
57
GND
-
Ground terminal (digital system)
58
H_DIOR_N
I
Read signal input from the CPU
59
H_DIOW_N
I
Write signal input from the CPU
60
H_DMARQ
O
Request signal output to the CPU
61 to 64
H_DD15, H_DD0,
H_DD14, H_DD1
I/O
Two-way data bus with the CPU
NAS-S55HDE/SS-S55HDE
75
MOTHER BOARD IC9201 D610A003BZDP225 (AUDIO DSP)
Pin No.
Pin Name
I/O
Description
A1, A2
GND
-
Ground terminal
A3
CLKIN
I
Clock signal (25 MHz) input from the clock generator
A4
D1.2V
-
Power supply terminal (+1.2V)
A5
RSV
-
Not used
A6
TCK
-
Not used
A7
TDI
-
Not used
A8
TDO
-
Not used
A9, A10
D1.2V
-
Power supply terminal (+1.2V)
A11
GND
-
Ground terminal
A12
OSCV
-
Not used
A13
DSPRST#
I
Reset signal input from the CPU and audio DSP interface "L": reset
A14
GND
-
Ground terminal
A15, A16
HD13, HD11
I/O
Two-way data bus with the audio DSP interface
A17
D3.3V
-
Power supply terminal (+3.3V)
A18
HD7
I/O
Two-way data bus with the audio DSP interface
A19, A20
GND
-
Ground terminal
B1
GND
-
Ground terminal
B2
D1.2Ｖ
-
Power supply terminal (+1.2V)
B3
D3.3V
-
Power supply terminal (+3.3V)
B4, B5
RSV
-
Not used
B6
TRST#
-
Not used
B7
TMS
-
Not used
B8
D3.3V
-
Power supply terminal (+3.3V)
B9, B10
EMU1, EMU3
-
Not used
B11
OSCG
-
Not used
B12
EMU5
-
Not used
B13
D3.3V
-
Power supply terminal (+3.3V)
B14
HD15
I/O
Two-way data bus with the audio DSP interface
B15
GND
-
Ground terminal
B16 to B18
HD10, HD8, HD5
I/O
Two-way data bus with the audio DSP interface
B19
D1.2V
-
Power supply terminal (+1.2V)
B20
GND
-
Ground terminal
C1
SCL
O
I2C serial clock signal output to the EEPROM
C2
WP
O
Write protect signal output to the EEPROM
C3
D1.2V
-
Power supply terminal (+1.2V)
C4
CLKMODE0
I
PLL clock setting terminal
C5
PLLHV
-
Power supply terminal (+3.3V)
C6
AGND
-
Ground terminal
C7
D1.2V
-
Power supply terminal (+1.2V)
C8, C9
GND
-
Ground terminal
C10
D3.3V
-
Power supply terminal (+3.3V)
C11
EMU4
-
Not used
C12
OSCO
-
Not used
C13
NMI
-
Not used
C14 to
C17
HD14, HD12, HD9,
HD6
I/O
Two-way data bus with the audio DSP interface
C18
D1.2V
-
Power supply terminal (+1.2V)
C19, C20
HD4, HD3
I/O
Two-way data bus with the audio DSP interface
D1
D3.3V
-
Power supply terminal (+3.3V)
D2
SDA
I/O
Two-way I2C serial data bus with the EEPROM
D3
EMU2
-
Not used
D4
GND
-
Ground terminal
D5, D6
D1.2V
-
Power supply terminal (+1.2V)
D7
RSV
-
Not used
D8
GND
-
Ground terminal
D9
ENU0
-
Not used
D10
CLKO3
-
Not used
D11
D1.2V
-
Power supply terminal (+1.2V)
D12
OSCI
I
Not used
NAS-S55HDE/SS-S55HDE
76
Pin No.
Pin Name
I/O
Description
D13
GND
-
Ground terminal
D14, D15
D1.2V
-
Power supply terminal (+1.2V)
D16
D3.3V
-
Power supply terminal (+3.3V)
D17
GND
-
Ground terminal
D18
HD2
I/O
Two-way data bus with the audio DSP interface
D19
D3.3V
-
Power supply terminal (+3.3V)
D20
HD1
I/O
Two-way data bus with the audio DSP interface
E1
CLKS1
I
Not used
E2
GND
-
Ground terminal
E3
RSV
-
Not used
E4
GND
-
Ground terminal
E17
GND
-
Ground terminal
E18
HAS#
-
Not used
E19
HDS1#
I
Data strobe signal input from the audio DSP interface
E20
HD0
I/O
Two-way data bus with the audio DSP interface
F1
AXR0-4
I
Serial data input from the input selector
F2
AHCLKX0
-
Not used
F3
D3.3V
-
Power supply terminal (+3.3V)
F4
D1.2V
-
Power supply terminal (+1.2V)
F17
D1.2V
-
Power supply terminal (+1.2V)
F18
HDS2#
I
Data strobe signal input from the audio DSP interface
F19
GND
-
Ground terminal
F20
HCS#
O
Chip select signal output to the audio DSP interface
G1
AXR0-2
O
Serial data output to the stream processor
G2
AXR0-3
-
Not used
G3
ACLKX0
I
Bit clock signal input from the input selector
G4
GND
-
Ground terminal
G17
GND
-
Ground terminal
G18, G19
HCNTL0, HCNTL1
I
Control signal input from the audio DSP interface
G20
HR/W#
I
Data write/read changeover signal input from the audio DSP interface
H1
AFSX0
I
L/R sampling clock signal input from the input selector
H2
AXR0-1
O
Serial data output to the input selector
H3
ACLKR0
-
Not used
H4
GND
-
Ground terminal
H17
GND
-
Ground terminal
H18
D3.3V
-
Power supply terminal (+3.3V)
H19
XHRDY
O
Ready signal output to the audio DSP interface
H20
HHWIL
I
Half word signal input from the audio DSP interface
J1
AXR0-0
-
Not used
J2
D3.3V
-
Power supply terminal (+3.3V)
J3
AFSR0
-
Not used
J4
GND
-
Ground terminal
J9 to J12
GND
-
Ground terminal
J17
HOLD#
-
Not used
J18
HOLDA#
-
Not used
J19
BUSREQ
-
Not used
J20
HINT#
O
Interrupt request signal output to the audio DSP interface
K1
D1.2V
-
Power supply terminal (+1.2V)
K2
GND
-
Ground terminal
K3
AHCLKR0
-
Not used
K4
D1.2V
-
Power supply terminal (+1.2V)
K9 to K12
GND
-
Ground terminal
K17
D1.2V
-
Power supply terminal (+1.2V)
K18, K19
ED0, ED1
I/O
Two-way data bus with the SD-RAM
K20
GND
-
Ground terminal
L1
FSX1
-
Not used
L2
DX1
-
Not used
L3
CLKX1
-
Not used
L4
D1.2V
-
Power supply terminal (+1.2V)
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