DOWNLOAD Sony NAS-S55HDE / NAS-SC55PKE / SS-S55HDE Service Manual ↓ Size: 10 MB | Pages: 106 in PDF or view online for FREE

Model
NAS-S55HDE NAS-SC55PKE SS-S55HDE
Pages
106
Size
10 MB
Type
PDF
Document
Service Manual
Brand
Device
Audio
File
nas-s55hde-nas-sc55pke-ss-s55hde.pdf
Date
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Sony NAS-S55HDE / NAS-SC55PKE / SS-S55HDE Service Manual ▷ View online

NAS-S55HDE/SS-S55HDE
69
Pin No.
Pin Name
I/O
Description
342
MODE3
I
Bus mode setting terminal
343
MODE0
I
Clock operation mode setting terminal
344
TXD1
O
Not used
345
AUDATA1
O
Not used
346
XCS0
O
Chip select signal output to the HDD driver and CD-ROM drive
347
DA1
O
Address signal output to the HDD driver and CD-ROM drive
348
XDMACK
O
Acknowledge signal output to the HDD driver and CD-ROM drive
349
XDIOR
O
Read signal output to the HDD driver and CD-ROM drive
350
DMARQ
I
Request signal input from the HDD driver and CD-ROM drive
351 to 353
DD1, DD3, DD5
I/O
Two-way data bus with the HDD driver and CD-ROM drive
354
XBS
O
Not used
355
XRD
O
Output enable signal output to the fl ash memory
356
IDERST
O
Reset signal output to the HDD driver and CD-ROM drive    "L": reset
357
VSSPLL2
-
Ground terminal
358
VSSCA
-
Ground terminal
359
VCCA
-
Power supply terminal (+3.3V)
360
VSSCA1
-
Ground terminal
361
PA3
O
Reset signal output to the HDD driver
362
VDDQ
-
Power supply terminal (+3.3V)
363
MODE6
I
PCI operation mode setting terminal    
"L": host mode, "H": target mode    Fixed at "H" in this set
364
MODE4
I
Bus mode setting terminal
365
MODE1
I
Clock operation mode setting terminal
366
AUDSYNC
O
Not used
367
TDO
O
Not used
368
TMS
I
Not used
369
TRST
I
Not used
370
DA2
O
Address signal output to the HDD driver and CD-ROM drive
371 to 374
DD14, DD12, DD10, 
DD8
I/O
Two-way data bus with the HDD driver and CD-ROM drive
375
TEST-IN-HIGH
I
Input terminal for the test (fi xed at "H")
376
NMI
I
Not used
377
DSPCLK
I
Clock signal (54 MHz) input from the clock generator
378
XTAL
O
System clock (25 MHz) output terminal
379
VSSPLL1
-
Ground terminal
380
VSSCA
-
Ground terminal
381
CBU1
O
Phase amends capacity connection terminal
382
DAC
O
Chroma signal output to the video amplifi er
383
VDDQ
-
Power supply terminal (+3.3V)
384
SCL
O
Serial clock signal output to the EEPROM
385
SDA
I/O
Two-way data bus with the EEPROM
386
MODE5
I
Endian setting terminal
387
MODE2
I
Clock operation mode setting terminal
388
ASEBRK
O
Not used
389
TCK
I
Not used
390
TDI
I
Not used
391
XCS1
O
Chip select signal output to the HDD driver and CD-ROM drive
392 to 395
DD15, DD13, DD11, 
DD9
I/O
Two-way data bus with the HDD driver and CD-ROM drive
396
DIR
O
Not used
397
NC
-
Not used
398
RESET
I
Reset signal input from the system controller    "L": reset
399
RDY
O
Not used
400
EXTAL
I
System clock (25 MHz) input terminal
401
VDDPLL1
-
Power supply terminal (+1.2V)
402
DACVBS
O
Component video signal output to the video amplifi er
403
DAY
O
Y signal output to the video amplifi er
404
REXT
I
Reference resistor input terminal
NAS-S55HDE/SS-S55HDE
70
MOTHER BOARD  IC3001  RTL8100CL-LF (ETHERNET INTERFACE)  
 
Pin No.
Pin Name
I/O
Description
1, 2
TX+, TX-
O
Transmit data output to the network connector
3
AVDD33
-
Power supply terminal (+3.3V)
4
GND
-
Ground terminal
5, 6
RX+, RX-
I
Receive data input from the network connector
7
AVDD33
-
Power supply terminal (+3.3V)
8
CTRL25
O
+2.5V power supply control signal output terminal
9 to 11
NC
-
Not used
12
AVDD25
-
Power supply terminal (+2.5V)
13 to 16
NC
-
Not used
17
GND
-
Ground terminal
18, 19
NC
-
Not used
20
AVDD33 (REG0)
-
Power supply terminal (+3.3V)
21
GND
-
Ground terminal
22
NC
-
Not used
23
ISOLATEB
I
Not used
24
NC
-
Not used
25
INTAB
O
Interrupt signal output to the CPU
26
VDD33
-
Power supply terminal (+3.3V)
27
PCIRSTB
I
Reset signal input from the CPU
28
PCICLK
I
Clock signal (33.3 MHz) input from the CPU and clock generator
29
GNTB
I
Grant signal input from the CPU
30
REQB
O
Request signal output to the CPU
31
PMEB
O
Not used
32
VDD25
-
Power supply terminal (+2.5V)
33, 34
AD31, AD30
I/O
Address signal and data input/output with the ethernet interface, CPU and audio DSP inter-
face
35
GND
-
Ground terminal
36, 37
AD29, AD28
I/O
Address signal and data input/output with the ethernet interface, CPU and audio DSP inter-
face
38
GND
-
Ground terminal
39, 40
AD27, AD26
I/O
Address signal and data input/output with the ethernet interface, CPU and audio DSP inter-
face
41
VDD33
-
Power supply terminal (+3.3V)
42, 43
AD25, AD24
I/O
Address signal and data input/output with the ethernet interface, CPU and audio DSP inter-
face
44
CBEB3
I/O
Command and byte enable signal input/output with the ethernet interface, CPU and audio 
DSP interface
45
NC
-
Not used
46
IDSEL
I
Initialization device switch signal input from the CPU
47
AD23
I/O
Address signal and data input/output with the ethernet interface, CPU and audio DSP inter-
face
48
NC
-
Not used
49, 50
AD22, AD21
I/O
Address signal and data input/output with the ethernet interface, CPU and audio DSP inter-
face
51, 52
GND
-
Ground terminal
53
AD20
I/O
Address signal and data input/output with the ethernet interface, CPU and audio DSP inter-
face
54
VDD25
-
Power supply terminal (+2.5V)
55
AD19
I/O
Address signal and data input/output with the ethernet interface, CPU and audio DSP inter-
face
56
VDD33
-
Power supply terminal (+3.3V)
57 to 59
AD18 to AD16
I/O
Address signal and data input/output with the ethernet interface, CPU and audio DSP inter-
face
60
CBEB2
I/O
Command and byte enable signal input/output with the ethernet interface, CPU and audio 
DSP interface
61
FRAMEB
I/O
Frame signal input/output with the ethernet interface, CPU and audio DSP interface
62
NC
-
Not used
63
IRADYB
I/O
Initiator ready signal input/output with the ethernet interface, CPU and audio DSP interface
64
NC
-
Not used
65
CLKRUNB
I/O
Not used
66
GND
-
Ground terminal
NAS-S55HDE/SS-S55HDE
71
Pin No.
Pin Name
I/O
Description
67
TRDYB
I/O
Target ready signal input/output with the ethernet interface, CPU and audio DSP interface
68
DEVSELB
I/O
Device changeover signal input/output with the ethernet interface, CPU and audio DSP 
interface
69
STOPB
I/O
Stop signal input/output with the ethernet interface, CPU and audio DSP interface
70
PERRB
I/O
Parity error signal input/output with the ethernet interface, CPU and audio DSP interface
71
VDD33
-
Power supply terminal (+3.3V)
72 to 74
NC
-
Not used
75
SERRB
I/O
System error signal input/output with the ethernet interface, CPU and audio DSP interface
76
PAR
I/O
Parity signal input/output with the ethernet interface, CPU and audio DSP interface
77
CBEB1
I/O
Command and byte enable signal input/output with the ethernet interface, CPU and audio 
DSP interface
78
VDD25
-
Power supply terminal (+2.5V)
79
AD15
I/O
Address signal and data input/output with the ethernet interface, CPU and audio DSP inter-
face
80, 81
GND
-
Ground terminal
82, 83
AD14, AD13
I/O
Address signal and data input/output with the ethernet interface, CPU and audio DSP inter-
face
84
VDD33
-
Power supply terminal (+3.3V)
85 to 87
AD12 to AD10
I/O
Address signal and data input/output with the ethernet interface, CPU and audio DSP inter-
face
88
NC
-
Not used
89, 90
AD9, AD8
I/O
Address signal and data input/output with the ethernet interface, CPU and audio DSP inter-
face
91
GND
-
Ground terminal
92
CBEB0
I/O
Command and byte enable signal input/output with the ethernet interface, CPU and audio 
DSP interface
93
AD7
I/O
Address signal and data input/output with the ethernet interface, CPU and audio DSP inter-
face
94
VDD33
-
Power supply terminal (+3.3V)
95 to 98
AD6 to AD3
I/O
Address signal and data input/output with the ethernet interface, CPU and audio DSP inter-
face
96
SRCLK
O
Not used
97
SRMOD
I
Not used
98
SRDTA
I/O
Not used
99
VDD25
-
Power supply terminal (+2.5V)
100, 101
GND
-
Ground terminal
102 to 104
AD2 to AD0
I/O
Address signal and data input/output with the ethernet interface, CPU and audio DSP inter-
face
105
LANWAKE
O
Not used
106
EECS
O
Chip select signal output to the EEPROM
107
VDD33
-
Power supply terminal (+3.3V)
108
EEDO
I
Serial data input from the EEPROM
109
AUX/EEDI
O
Serial data output to the EEPROM
110
NC
-
Not used
111
EESK
O
Serial data transfer clock signal output to the EEPROM
112, 113
NC
-
Not used
114, 115
LED2, LED1
O
Not used
116
NC
-
Not used
117
LED0
O
Not used
118
NC
-
Not used
119
GND
-
Ground terminal
120
NC
-
Not used
121
XTAL1
I
Clock signal (25 MHz) input from the clock generator
122
XTAL2
O
Not used
123, 124
GND
-
Ground terminal
125, 126
NC
-
Not used
127
RSET
-
Not used
128
GND
-
Ground terminal
NAS-S55HDE/SS-S55HDE
72
MOTHER BOARD  IC4001  uPD720101GJ-UEN-E2-A (USB INTERFACE) 
 
 
Pin No.
Pin Name
I/O
Description
1, 2
VDD
-
Power supply terminal (+3.3V)
3
OCI1
I
Over current detection signal input terminal
4
PPON1
O
Not used
5
OCI2
I
Over current detection signal input terminal
6
PPON2
O
Not used
7
OCI3
I
Over current detection signal input terminal
8
PPON3
O
Not used
9
OCI4
I
Over current detection signal input terminal
10
PPON4
O
Not used
11
OCI5
I
Over current detection signal input terminal
12
PPON5
O
Not used
13
VCCRST0
I
Not used
14
PME0
O
Not used
15
PCLK
I
Clock signal (33.3 MHz) input from the CPU and clock generator
16
VBBRST0
I
Reset signal input from the CPU    "L": reset
17
VDD_PCI
-
Power supply terminal (+3.3V)
18
VSS
-
Ground terminal
19
VDD
-
Power supply terminal (+3.3V)
20 to 22
INTA0 to INTC0
O
Interrupt signal output to the CPU
23
GNT0
I
Grant signal input from the CPU
24
REQ0
O
Request signal output to the CPU
25 to 32
AD31 to AD24
I/O
Address signal and data input/output with the ethernet interface, CPU and audio DSP inter-
face
33
CBE30
I/O
Command and byte enable signal input/output with the ethernet interface, CPU and audio 
DSP interface
34
IDSEL
I
Initialization device switch signal input from the CPU
35
VSS
-
Ground terminal
36
VDD
-
Power supply terminal (+3.3V)
37, 38
VSS
-
Ground terminal
39 to 42
AD23 to AD20
I/O
Address signal and data input/output with the ethernet interface, CPU and audio DSP inter-
face
43
VDD
-
Power supply terminal (+3.3V)
44 to 47
AD19 to AD16
I/O
Address signal and data input/output with the ethernet interface, CPU and audio DSP inter-
face
48
CBE20
I/O
Command and byte enable signal input/output with the ethernet interface, CPU and audio 
DSP interface
49
FRAME0
I/O
Frame signal input/output with the ethernet interface, CPU and audio DSP interface
50
IRDY0
I/O
Initiator ready signal input/output with the ethernet interface, CPU and audio DSP interface
51
TRDY0
I/O
Target ready signal input/output with the ethernet interface, CPU and audio DSP interface
52
DEVSEL0
I/O
Device changeover signal input/output with the ethernet interface, CPU and audio DSP 
interface
53
STOP0
I/O
Stop signal input/output with the ethernet interface, CPU and audio DSP interface
54
VSS
-
Ground terminal
55
VDD
-
Power supply terminal (+3.3V)
56
VDD_PCI
-
Power supply terminal (+3.3V)
57
PERR0
I/O
Parity error signal input/output with the ethernet interface, CPU and audio DSP interface
58
SERR0
I/O
System error signal input/output with the ethernet interface, CPU and audio DSP interface
59
PAR
I/O
Parity signal input/output with the ethernet interface, CPU and audio DSP interface
60
CBE10
I/O
Command and byte enable signal input/output with the ethernet interface, CPU and audio 
DSP interface
61 to 68
AD15 to AD8
I/O
Address signal and data input/output with the ethernet interface, CPU and audio DSP inter-
face
69
CBE00
I/O
Command and byte enable signal input/output with the ethernet interface, CPU and audio 
DSP interface
70
AD7
I/O
Address signal and data input/output with the ethernet interface, CPU and audio DSP inter-
face
71, 72
VSS
-
Ground terminal
73, 74
VDD
-
Power supply terminal (+3.3V)
75 to 79
AD6 to AD2
I/O
Address signal and data input/output with the ethernet interface, CPU and audio DSP inter-
face
80
VDD_PCI
-
Power supply terminal (+3.3V)
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