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33

0 dB=0.775 V

1. Desmagnetize a cabeça de reprodução e gravação com um des-

magnetizador de cabeças. 

2. 2. Não use chaves imantadas durante o ajuste. 
3. Depois de fazer os ajustes, aplique o lacre nos componentes pa-

ra garantir o ajuste executado. 

4. Os ajustes devem ser executados com tensão de alimentação 

dentro do especificado. 

5. Os ajustes devem ser feitos na ordem indicada nesse manual. 

Como regra geral, o circuito do toca-fitas deve ser completamen-
te ajustado antes de se colocar lacre nas peças ajustadas. 

6. Os ajustes devem ser executados em ambos os canais, direito 

e esquerdo. 

7. Chaves e controles devem ser posicionados conforme especificado. 

• Fita de Teste

 Execute este ajuste para ambos os decks. 

Procedimento:
1. Modo:  Reprodução (Playback)

P-4-A063 6.3 kHz, –10 dB Ajuste de Azimuth 

set

Placa Principal 
IC101
Pino 28 (L-CH)
Pino 37 (R-CH)

Placa Principal 
IC101
Pin 38 (GND)

+

–

medidor de nível 

fita de teste 
P-4-A063
(6.3 kHz, –10 dB)

oscilloscopio

set

J802

SAÍDA DE VIDEO 

75 

Ω

1.00 

±

 0.05 Vp-p

(BRANCO 100%)

Este ajuste atende as especificações do padrão NTSC e se 
não ajustado corretamente, o brilho será excessivo ou escuro. 

Procedimento: 
1. Conecte o osciloscópio na saída de VIDEO. 
2. Reproduza o DVD de referência . 
3. Verifique se o sinal de vídeo é 1.00±0.05Vp-p. 

Para decisão de substituição da unidade ótica por falha, verifique 
 “DECISÃO DE SUBSTITUIÇÃO DA UNIDADE ÓTICA POR
FALHA” (ver a página 8)

Use os discos de teste abaixo para o modo de teste.
LUV-P01 (CD):

PART No. 4-999-032-01

TDV-520CSO (DVD-SL): PART No. J-2501-236-A
TDV-540C (DVD-DL):

PART No. J-2501-235-A

 Não utilize disco de teste existente..

Após reparo das peças no circuito de servo (RF amplifier (IC001), DSP
(IC509), motor driver (IC501), EEPROM (IC903) so on) are
substituidas, o reajuste do circuito de servo é necessário. Selecione “ALL”
em  “1. DRIVE AUTO ADJUSTMENT” (Refer to page 8 in TEST
MODE) e ajuste o DVD-SL simples camadar), CD and DVD-DL 
dupla camada).

34

2. Gire o parafuso de ajuste e verifique o pico de saída. Se os picos

não forem iguais para os dois canais ajuste o parafuso para 
que os dois tenham 1dB de valor de pico. 

3. Modo: Reprodução ( Playback) 

4. Após os ajustes aplique o lacre adequado sobre os compo-

nentes ajustados. 

Posição do 

parafuso

L-CH
pico

dentro de

1dB

nivel de

saida

L-CH
pico

R-CH
pico

dentro de
1dB

Posição do 

parafuso

R-CH
pico

MAIN
board
IC101

fita de teste
P-4-A063
(6.3 kHz, –10 dB)

pino 37

oscilloscope

L-CH

R-CH

V

H

forma de onda no osciloscpio 

in phase 45

°

90

°

135

°

180

°

bom ruim

pino 38

pino 28

L

R

reverse

forward

Localização do Ajuste: Cabeça Reprodutora (Deck A). 

Cabeça Reprodutora/Apagadora/Gravadora (Deck B). 

35

Pin No.

Pin Name

I/O

Pin Description

1, 2

D5, D6

I/O

Two-way data bus signal input from/output to mechanism control IC.

3

VSS

—

Ground pin

4

D7

I/O

Two-way data bus signal input from/output to mechanism control IC.

5

A0

I/O

Address signal input from/output to mechanism control IC.

6

VDD

—

Power supply pin (+3.2 V)

7

A1

I/O

Address signal input from/output to mechanism control IC.

8

VDD5V

—

Power supply pin (+5 V)

9 to 14

A2 to A7

I/O

Address signal input from/output to mechanism control IC.

15

VSS

—

Ground pin

16

XWAIT

O

Not used in this set. (Open)

17

XRD

I

Read strobe signal input from mechanism control IC.

18

XWR

I

Write strobe signal input from mechanism control IC.

19

XCS

I

Chip select signal input from mechanism control IC.

20, 21

XINT0, XINT1

O

Interrupt signal output to mechanism control IC.

22

VDD

—

Power supply pin (+3.2 V)

23

XHRS

I

Not used in this set. (Open)

24

HDB7

I/O

Stream data input from/output to DVD system processor IC.

25

VSS

—

Ground pin

26

HDB8

I/O

Error flag signal input from/output to DVD system processor IC.

27

HDB6

I/O

Stream data input from/output to DVD system processor IC.

28

VDDS

—

Power supply pin (+5 V)

29

HDB9

I/O

Not used in this set. (Open)

30

HDB5

I/O

Stream data input from/output to DVD system processor IC.

31

HDBA

I/O

Not used in this set. (Open)

32

HDB4

I/O

Stream data input from/output to DVD system processor IC.

33

VSS

—

Ground pin

34

HDBB

I/O

Not used in this set. (Open)

35

HDB3

I/O

Stream data input from/output to DVD system processor IC.

36

VDD

—

Power supply pin (+3.2 V)

37

HDBC

I/O

Not used in this set. (Open)

38

VDDS

—

Power supply pin (+5 V)

39

HDB2

I/O

Stream data input from/output to DVD system processor IC.

40

HDBD

I/O

Not used in this set. (Open)

41

HDB1

I/O

Stream data input from/output to DVD system processor IC.

42

VSS

—

Ground pin

43

HDBE

I/O

Not used in this set. (Open)

44

HDBO

I/O

Stream data input from/output to DVD system processor IC.

45

HDBF

I/O

Not used in this set. (Open)

46

HDRQ

O

Serial data effect flag signal output to DVD system processor IC.

47

VDDS

—

Power supply pin (+5 V)

48

XHWR

I

Serial data transfer clock signal input from DVD system processor IC.

49

XHRD

I

Not used in this set. (Open)

50

VDD

—

Power supply pin (+3.2 V)

51

REDY

O

Not used in this set. (Open)

52

VSS

—

Ground pin

53

XHAC

I

Serial data request signal input from DVD system processor IC. (DVD mode)

54

HINT

I/O

Not used in this set. (Fixed at H.)

55

XS16

I

Not used in this set. (Fixed at H.)

56

HA1

I

Not used in this set. (Fixed at H.)

57

XPDI

I/O

Not used in this set. (Fixed at H.)

58

VDDS

—

Power supply pin (+5 V)

36

Pin No.

Pin Name

I/O

Pin Description

59, 60

HA0, HA2

I

Not used in this set. (Fixed at H.)

61

VSS

—

Ground pin

62, 63

HCS0, HCS1

I

Not used in this set. (Open)

64

VDD

—

Power supply pin (+3.2 V)

65

DASP

I/O

Not used in this set. (Fixed at H.)

66 to 69

MDB0 to MDB3

I/O

Two-way data bus signal input from/output to 16Mbit D-RAM IC.

70

VSS

—

Ground pin

71

MDB4

I/O

Two-way data bus signal input from/output to 16Mbit D-RAM IC.

72

VDD5V

—

Power supply pin (+5 V)

73 to 75

MDB5 to MDB7

I/O

Two-way data bus signal input from/output to 16Mbit D-RAM IC.

76

XMWR

O

Write enable signal output to 16Mbit D-RAM IC.

77

VDD

—

Power supply pin (+3.2 V)

78

XRAS

O

Row address strobe signal output to 16Mbit D-RAM IC.

79, 80

MA0, MA1

O

Address signal output to 16Mbit D-RAM IC.

81

VSS

—

Ground pin

82 to 87

MA2 to MA7

O

Address signal output to 16Mbit D-RAM IC.

88

VDD

—

Power supply pin (+3.2 V)

89

MA8

O

Address signal output to 16Mbit D-RAM IC.

90

VSS

—

Ground pin

91

MA9/mnt0

O

Address signal output to 16Mbit D-RAM IC.

92

MA10/mnt1

O

EEPROM ready signal output to mechanism control IC.

93

MA11/mnt2

O

Address signal output to 16Mbit D-RAM IC.

94

XMOE

O

Output enable signal output to 16Mbit D-RAM IC.

95

XCAS

O

Column address strobe signal output to 16Mbit D-RAM IC.

96, 97

MDB8, MDB9

I/O

Two-way data bus signal input from/output to 16Mbit D-RAM IC.

98

VSS

—

Ground pin

99

MDBA

I/O

Two-way data bus signal input from/output to 16Mbit D-RAM IC.

100

VDD

—

Power supply pin (+3.2 V)

101, 102

MDBB, MDBC

I/O

Two-way data bus signal input from/output to 16Mbit D-RAM IC.

103

VDD5V

—

Power supply pin (+5 V)

104 to 106

MDBD to MDBF

I/O

Two-way data bus signal input from/output to 16Mbit D-RAM IC.

107

GFS

O

Guard frame sync signal output to mechanism control IC.

108

VSS

—

Ground pin

109

APE0

O

Absolute phase error signal output

110

VDD

—

Power supply pin (+3.2 V)

111

DASY0

O

RF binary signal output

112

GNDA5

—

Ground pin

113, 114

ASF1, ASF2

O

Filter connected pin for selection the constant asymmetry compensation.

115

DASY1

I

Analog signal input after integrated from the RF binary signal.

116

RFDCC

I

Input pin for adjusting DC cut high-pass filter for RF signal.

117

RFIN

I

RF signal input from RS-232C. (for check)

118, 119

VCCA5, VCCA4

—

Power supply pin (+3.2 V)

120

VCOR1

I

VCO oscillating range setting resistor connected

121

VCOIN

I

VCO input

122, 123

GNDA4, GNDA3

—

Ground pin

124

LPF5

O

Inverted signal output to operation amplifier from PLL loop filter.

125

VC1

I

Middle point voltage (+1.65 V) input

126, 127

LPF2, LPF1

I

Inverted signal input from operation amplifier from PLL loop filter.

128, 129

VCCA3, VCCA2

—

Power supply pin (+3.2 V)

130

PD0

O

Signal output to charge pump for phase comparator.

131

PDHVCC

O

Middle point voltage output to RF PLL.

132

FDO

O

Signal output to charge pump for frequency comparator.

133, 134

GNDA2, GNDA1

—

Ground pin