Sony MHC-RG90 Service Manual ▷ View online
MHC-RG90�
49
49
F01
R02
R01
LINE NF
LINE IN
REFERENCE
CURRENT
REFERENCE
CURRENT
RESET
BAND
PASS
FILTER
DET
17
RESET
18
F02
16
F03
15
F04
14
F05
13
F06
12
REC LEVEL
11
VCC
10
4
3
2
1
+
–
REC NF
REC IN
6
RESET C
7
BIAS C
8
GND
9
5
+
–
1
2
3
4
5
6
7
8
9
CONTROL LOGIC
TSD
VREF
OUT2
OUT1
RNF
VM
VCC
FIN
GND
RIN
RW/ROM
RW/ROM
EQ ON/OFF
VOFST
VOFST
DVC
VC
VC
VC
RW/ROM
VC
DVC
30
29
28
+
–
+
–
DVC
VCC
DVC
27
26
25
24
RW/ROM
EQ
23
22
21
20
19
RFAC
VCA
VCC
+
–
DVC
+
–
+
–
RW/ROM
VC
RW/ROM
DVC
+
–
3
A
B
C
D
B
C
C
A
A
A
B
C
C
D
B
C D
D
+
–
1
2
APC AMP
5
6
7
8
9
4
RFAC
SUMMING
AMP
RW/ROM
APC-OFF
(Hi-Z)
RW/ROM
(H/L)
VOFST
VC
RW/ROM
+
–
10
11
GM
GM
18
17
16
B
D
A
C
13
14
15
12
EQ IN
LD
PD
GND
A
B
C
D
AC SUM
E
F
DVCC
DVC
RFAC
SW
DC OFST
RFDCI
RFDCO
VC
RFC
VFC
BST
RFG
VCC
CEI
CE
TE BAL
TE
FEI
FE
• DIAGRAMA EM BLOCO DOS IC's
– Placa BD –
– Placa BD –
IC101
CXD3017Q
IC102
BA5974FM-E2
IC103
CXA2581N-T4
– Placa DRIVER –
IC701
BA6956AN
– Placa PAINEL –
IC602
BA3830F-E2
TE
RFDC
CE
IGEN
AVSS0
ADIO
AVDD0
CLTV
FILO
AVSS3
VSS
AVDD3
DOUT
VDD
PCO
FILI
ASYO
ASYI
RFAC
BIAS
SSTP
DFCT
MIRR
MDP
LOCK
FOK
SFDR
VSS
TEST
FRDR
FE
VC
VC
COUT
SE
XTSL
TES1
SRDR
TFDR
FFDR
TRDR
TRDR
2
1
70
71
68
69
66
67
64
65
62
61
63
73
74
72
75
76
77
78
79
80
4
XRST
3
SQCK
SQSO
5
9
8
7
6
56
60
53
54
55
59
57
58
51
52
48
49
50
47
44
45
46
43
41
42
XLAT
CLOK
SENS
SYSM
DATA
XUGF
XPCK
GFS
C2PO
WFCK
10 11 12 13 14 15 16 17 18 19 20
21
22
23
24
25
26
32
33
30
31
36
37
34
35
39
40
38
28
27
29
SPOA
ATSK
SCLK
VDD
SCOR
SPOB
XLON
XTAI
XVDD
EMPH
AVDD1
AOUT1
AIN1
XTAO
XVSS
XVSS
AIN2
AOUT2
AVDD2
RMUT
LOUT2
LOUT1
BCK
LRCK
PCMD
LMUT
AVSS1
AVSS2
CPU
INTERFACE
SERVO AUTO
SEQUENCER
SERIAL IN
INTERFACE
OVER SAMPLING
DIGITAL FILTER
3rd ORDER
NOISE SHAPER
PWM
PWM
EFM
DEMODULATOR
TIMING
LOGIC
DIGITAL
OUT
D/A
INTERFACE
DIGITAL
PLL
ASYMMETRY
CORRECTOR
CLOCK
GENERATOR
MIRR, DFCT,
FOK
DETECTOR
DIGITAL
CLV
SUBCODE
PROCESSOR
SERVO
INTERFACE
SERVO DSP
FOCUS
SERVO
SERVO
TRACKING
SERVO
SLED
SERVO
PWM GENERATOR
FOCUS PWM
GENERATOR
TRACKING
PWM GENERATOR
SLED PWM
GENERATOR
16K
RAM
ERROR
CORRECTOR
INTERNAL BUS
A/D
CONVERTER
OPERATIONAL
AMPLIFIER
ANALOG SWITCH
LEVEL SHIFT
INTERFACE
INTERFACE
INTERFACE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
20
21
22
23
24
25
26
27
28
19
18
17
16
15
F
R
R
F
F
R
R
F
R
R
F
F
MUTE
THERMAL
SHUTDOWN
VREFOUT
VREFIN
POWVCC
CH1FIN
CH1RIN
CH2FIN
CH2RIN
CH2OUTR
CH2OUTF
CH1OUTR
CH1OUTF
CAP
AIN1
CAP
AIN2
GND
PRFVCC
MUTE
POWVCC
CH4SIN'
CH4SIN
CH4BIN
CH3FIN
CH3RIN
CH3OUTR
CH3OUTF
CH4OUTR
CH4OUTF
CAP
AIN3
GND
MHC-RG90�
7-28. DESCRIÇÃO DOS PINOS DOS IC's
•
PLACA PRINCIPAL IC501 M30620MCN-A00FP (SYSTEM CONTROLLER (CD MECHANISM CONTROL))
Pin No.
Pin Name
I/O
Description
1
NO-USE
—
Not used
2
STEREO
I
FM stereo detection signal input from the tuner unit “L”: stereo
3
TUNED
I
Tuning detection signal input from the tuner unit “L”: tuned
4
SIRCS
I
Remote control signal input
5 to 7
SUR1 to SUR3
O
Surround signal processor control signal output terminal Not used
8, 9
GND
—
Ground terminal
10
XC-IN
I
Sub system clock input terminal (32.768 kHz)
11
XC-OUT
O
Sub system clock output terminal (32.768 kHz)
12
RESET
I
System reset signal input from the reset signal generator “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
13
X-OUT
O
Main system clock output terminal (16 MHz)
14
VSS
—
Ground terminal
15
X-IN
I
Main system clock input terminal (16 MHz)
16
VCC
—
Power supply terminal (+3.3V)
17
NMI
I
Non-maskable interrupt input terminal
18
NO-USE
—
Not used
19
SCOR
I
Subcode sync (S0+S1) detection signal input from the digital signal processor
20
AC-CUT
I
AC off detection signal input from the reset signal generator “L”: AC cut checked
21
ST-MUTE
O
Tuner muting on/off control signal output “H”: muting on
22
ST-CE
O
PLL chip enable signal output to the tuner unit
23
ST-DOUT
O
PLL serial data output to the tuner unit
24
PWM3
O
RFDC PWM signal output to the RF amplifier (for CD-RW)
25
ST-DIN
I
PLL serial data input from the tuner unit
26
PWM2
O
PWM signal output to the RF amplifier (for CD-RW)
27
ST-CLK
O
PLL serial data transfer clock signal output to the tuner unit
28
PWM1
O
Focus servo drive PWM signal output to the RF amplifier (for CD-RW)
29
IIC-CLK
I/O
Communication data reading clock signal input or transfer clock signal output with the fluorescent
indicator tube driver
indicator tube driver
30
IIC-DATA
I/O
Communication data bus with the fluorescent indicator tube driver
31
TXD1
—
Not used
32
SQ-DATA
I
Subcode Q data input from the digital signal processor
33
SQ-CLK
O
Subcode Q data reading clock signal output to the digital signal processor
34
SENS
I
Internal status detection monitor input from the digital signal processor
35
CD-DATA
O
Serial data output to the digital signal processor
36
XLT
O
Serial data latch pulse output to the digital signal processor
37
CD-CLK
O
Serial data transfer clock signal output to the digital signal processor
38
CD-POWER
O
Power on/off control signal output for the CD section “H”: power on
39
CLOCK-OUT
O
Clock (32.768 kHz) signal output terminal (for test mode)
40
LD ON
O
Laser diode on/off control signal output to the RF amplifier “L”: laser diode on
41
GC RESET
I
Reset signal output to the fluorescent indicator tube driver “L”: reset
42
NO-USE
—
Not used
43
XRST
O
Reset signal output to the digital signal processor and motor/coil driver “L”: reset
44
LOAD-IN
O
Turn motor drive signal output
45
LOAD-OUT
O
Turn motor drive signal output
46
OPEN-SW
I
Disc tray open detection signal input terminal “L”: disc tray open
47
CLOSE-SW
I
Disc tray close detection signal input terminal “L”: disc tray close
50
MHC-RG90�
Pin No.
Pin Name
I/O
Description
48
BU UP/DOWN-SW
I
Optical pick-up up/down detection signal input terminal
49
TBL-SENS
I
Disc tray status detection signal input
50
CD-MUTE
O
CD analog signal muting on/off control signal output “H”: muting on
51
A-TRG
O
Deck-A side trigger plunger drive signal output “H”: plunger on
52
B-TRG
O
Deck-B side trigger plunger drive signal output “H”: plunger on
53
AMS-IN
I
Whether a music is present or not from the automatic music sensor circuit
“L”: music is present, “H”: music is not present
“L”: music is present, “H”: music is not present
54
CAPM-H/L
O
High/normal speed selection signal output “L”: high speed, “H”: normal speed
55
CAPM-CNT1
O
Capstan motor drive signal output
56
A-PLAY
I
Deck-A play detection signal input terminal “H”: deck-A play
57
B-PLAY
I
Deck-B play detection signal input terminal “H”: deck-B play
58
TC-MUTE
O
Line muting on/off control signal output to the automatic music sensor circuit “H”: muting on
59
SW-ON-LED
O
LED drive signal output terminal “H”: LED on Not used
60
SW-MATRIX-
SURR-2-LED
O
LED drive signal output terminal “H”: LED on Not used
61
REC-MUTE
O
Recording muting on/off control signal output “L”: muting on
62
VCC
—
Power supply terminal (+3.3V)
63
SOFT-TEST
O
Output terminal for the software test
64
VSS
—
Ground terminal
65
BIAS
O
Recording bias on/off control signal output “H”: bias on
66
EQ-H/N
O
Normal/high speed selection signal output “L”: normal speed, “H”: high speed
67
PB-A/B
O
Deck-A/B selection signal output “L”: deck-B, “H”: deck-A
68
ALC
O
Automatic limiter control signal output “H”: limiter on
69
TC-RELAY
O
Recording/playback selection signal output “L”: playback, “H”: recording
70
A-HALF
I
Deck-A cassette detection signal input terminal “L”: no cassette, “H”: cassette in
71
SW-LINK-LED
O
LED drive signal output terminal “H”: LED on Not used
72
SW-MATRIX-
SURR-1-LED
O
LED drive signal output terminal “H”: LED on Not used
73
DISPLAY-KEY
I
DISPLAY key input terminal
74
POWER-KEY
I
I/1 key input terminal
75
STBY-LED
O
LED drive signal output of the I/1 indicator “H”: LED on
76
AUDIO-OUT
GAME/VCD
O
Video out game/video CD selection signal output terminal “L”: video CD, “H”: game
Not used
Not used
77
AUDIO-OUT
ON/OFF
O
Audio out on/off control signal output terminal “H”: audio out on Not used
78
HP MUTE
O
Headphone muting on/off control signal output “L”: muting on
79
HP-DETECT
I
Connection detection signal input of the headphone jack
“L”: no connected, “H”: headphone connected
“L”: no connected, “H”: headphone connected
80
LINE-MUTE
O
Line muting on/off control signal output “H”: muting on
81
GEQ DATA
O
Serial data output to the audio signal processor
82
GEQ CLK
O
Serial data transfer clock signal output to the audio signal processor
83
STK-MUTE
O
Power amplifier on/off control signal output “L”: standby mode, “H”: power amplifier on
84
STBY-RELAY
O
Main power on/off control signal output “H”: power on
85
NO-USE
—
Not used
86
LINK-RELAY
O
Relay drive signal output for the surround speaker protect “H”: relay on Not used
87
FRONT-RELAY
O
Relay drive signal output for the front speaker protect “H”: relay on
88
PROTECTOR
I
Protect on/off detection signal input from the speaker protect circuit “L”: protect on
51
MHC-RG90�
Pin No.
Pin Name
I/O
Description
89
A-SHUT
I
Shut off detection signal input from the deck-A side reel pulse detector
90
B-SHUT
I
Shut off detection signal input from the deck-B side reel pulse detector
91
B-HALF
I
Deck-B cassette detection signal input terminal “L”: cassette in, “H”: no cassette
92
MODEL-IN
I
Model setting terminal
93
DEST-IN
I
Destination setting terminal
94
SW-AD-KEY
I
Key input terminal (A/D input) Not used
95
NO-USE
—
Not used
96
AVSS
—
Ground terminal (for analog system)
97
SW-RELAY
O
Relay drive signal output for the sub woofer out protect “H”: relay on Not used
98
VREF
I
Reference voltage (+3.3V) input terminal (for analog system)
99
AVCC
—
Power supply terminal (+3.3V) (for analog system)
100
NO-USE
—
Not used
52
Click on the first or last page to see other MHC-RG90 service manuals if exist.