Sony MDS-LSA1 Service Manual ▷ View online
65
• IC601 CXD3202AR AUDIO LINK(MAIN BOARD)
Pin. No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
Pin Name
VSS
512FSI
VSS
XREQO/I
ADTI
XLATI
ACKI
VSS
ADTO
XLATO
ACKO
VDD
BCKI
LRCKI
DATAI
VSS
DIN
DOUT
VDD
BCKO
LRCKO
DATAO
EOF
VSS
1/8OUT
SYTO
PLLCKI
VDD
256FSO
VSS
TRST
TCK
TDI
TENAI
TD0
VST
VSS
DATA15
DATA14
DATA13
DATA12
DATA11
DATA10
DATA9
DATA8
VDD
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
I/O
-
I
-
I/O
I
I
I
-
O
O
O
-
I
I
I
-
I
O
-
O
O
O
O
-
O
O
-
-
-
-
-
-
-
-
-
-
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Function
Ground.
512 fs input (used for flow control and ATRAC reception)
Ground.
ATRAC data request (Output for transmission, input for reception)
ATRAC transmission data input
ATRAC transmission data latch signal
ATRAC transmission clock
Ground.
ATRAC reception data
ATRAC reception data latch signal
ATRAC reception clock
Power supply.
Raw audio transmission bit clock
Raw audio transmission L/R clock (fs)
Raw audio transmission data
Ground.
IEC958 bi-phase data input
IEC958 bi-phase data output
Power supply.
Raw audio reception bit clock
Raw audio reception L/R clock (fs)
Raw audio reception data output
Raw audio reception data error flag
Ground.
Split PLL clock (256 fs) and output 1/8 fs (used for PLL Ref)
Clock information transmitted from transmitting side (1/8 fs)
256 fs clock created from transmitted SYT
Power supply.
Same as PLLCKI clock
Ground.
Fix test pin at left on board. (Conected to ground.)
Fix test pin at left on board. (Conected to ground.)
Test pin on board open
Test pin on board open
Test pin on board open
Conected to ground.
Ground.
Host interface data bus (Bit 15)
Host interface data bus (Bit 14)
Host interface data bus (Bit 13)
Host interface data bus (Bit 12)
Host interface data bus (Bit 11)
Host interface data bus (Bit 10)
Host interface data bus (Bit 9)
Host interface data bus (Bit 8)
Power supply.
Host interface data bus (Bit 7)
Host interface data bus (Bit 6)
Host interface data bus (Bit 5)
Host interface data bus (Bit 4)
Host interface data bus (Bit 3)
Host interface data bus (Bit 2)
Host interface data bus (Bit 1)
Host interface data bus (Bit 0)
66
Pin. No.
55
56
57
58
59
60
61
62
63 to 70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86 to 94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
Pin Name
VSS
XINT
XCS
XWR
XRD
ALE
XRDY
VDD
A0 to 7
VSS
INTL/XM16
VSS
D3
D2
D1
D0
VSS
CTL1
CTL0
LREQ
VDD
SYSCLK
VSS
XRESET
TS0 to 8
VDD
HCLKOUT
GNCLK
TS9
DQSY
C2PO
SBSO
EXCK
WFCK
SCOR
TS16
TS17
TS18
VSS
VDD
A10/TS32
A9/TS31
A8/TS30
A7/TS29
A6/TS28
A5/TS27
VSS
A4/TS26
A3/TS25
A2/TS24
A1/TS23
A0/TS22
XRAS/TS21
I/O
-
O
I
I
I
I
O
-
I
-
I
-
I/O
I/O
I/O
I/O
-
I/O
I/O
O
-
I
-
I
O
-
O
O
O
O
I
I
O
I
I
O
O
O
-
-
O
O
O
O
O
O
-
O
O
O
O
O
O
Function
Ground.
Interrupt signal transmitted to host. (Not used.)
Chip select signal from host
Write signal from host
Read signal from host
Address latch signal from host (enabled for M16); Fixed at
“
H
”
for Intel
Ready signal transmitted to host (L = Ready)
Power supply.
Address bit 0 (when Intel host interface is used)
Ground.
Type of host to which connection is to be established. (L = M16; H = Intel)
Ground.
PHY interface data bus bit 3.
PHY interface data bus bit 2.
PHY interface data bus bit 1.
PHY interface data bus bit 0.
Ground.
PHY interface control bus bit 1
PHY interface control bus bit 0
PHY interface request signal
Power supply.
PHY interface system clock (49.152 MHz)
Ground.
System reset
Test output. (Not used.)
Power supply.
Clock obtained by splitting SYSCLK (24.576 MHz) (Not used.)
Clock obtained by dividing NCLK in two (6.144 MHz) (Not used.)
Test output. (Not used.)
Ubit reception frame pulse
CD C2 error input. (Conected to ground.)
CD SubCode data. (Conected to ground.)
CD SubCode read clock. (Not used.)
SubCode frame signal. (Conected to ground.)
CD SubCode frame lead signal. (Conected to ground.)
“8-bit clock synchronized to 512 fsin (Output at address 30, bit 4 = 1) (Not used.)”
“L/R clock synchronized to 512 fsin(Output at address 30, bit 4 = 1) (Not used.)”
DRAM address bit 11. (Not used.)
Ground.
Power supply.
DRAM address bit 10. (Not used.)
DRAM address bit 9. (Not used.)
DRAM address bit 8. (Not used.)
DRAM address bit 7. (Not used.)
DRAM address bit 6. (Not used.)
DRAM address bit 5. (Not used.)
Ground.
DRAM address bit 4. (Not used.)
DRAM address bit 3. (Not used.)
DRAM address bit 2. (Not used.)
DRAM address bit 1. (Not used.)
DRAM address bit 0. (Not used.)
DRAM XRAS. (Not used.)
67
Pin. No.
123
124
125
126
127 to 134
135
136 to 143
144
Pin Name
XCAS/TS20
XOE/TS19
XWE
VSS
DT15 to 8
VDD
DT7 to 0
VSS
I/O
O
O
O
-
I/O
-
I/O
-
Function
DRAM XCAS. (Not used.)
DRAM XOE. (Not used.)
DRAM XWE. (Not used.)
Ground.
DRAM data bit 15 to 8. (Not used.)
Power supply.
DRAM data bit 7 to 0. (Not used.)
Ground.
68
Pin. No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46 to 48
49
50
51
52
53
54
55
Pin Name
PC1
PC2
DVSS
DVSS
LPS
LREQ
DVDD
SCLK
DVSS
CTL0
CTL1
DVDD
DATAO
DATA1
DVSS
DATA2
DATA3
DVDD
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVDD
DVDD
DVSS
PURB
AVDD
AVSS
AVDD
XO
XI
AVSS
AVSS
AVSS
AVDD
LF
VCOR
AVSS
VREF
REXT
CPS
AVSS
AVDD
TBIAS2 to 0
TB2N
TB2P
TA2N
TA2P
TB1N
TB1P
TA1N
I/O
I
I
-
-
I
I
-
O
-
I/O
I/O
-
I/O
I/O
-
I/O
I/O
-
-
-
-
-
-
-
-
-
-
I
-
-
-
O
I
-
-
-
-
O
I
-
I
I
I
-
-
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Function
Connected to ground.
Connected to ground.
Ground.
Ground.
Link power status. Indicates whether link power is off or on. L: OFF H: ON
Link request. Link issues a PHY register read, write, or bus request through LREQ pin.
Power supply.
49.152 MHz link system clock.PHY-Link interface and cable interface synchronized with SCLK.
Ground.
PHY-Link interface control signals.
PHY-Link interface control signals.
Power supply.
PHY-Link interface data signals.
PHY-Link interface data signals.
Ground.
PHY-Link interface data signals.
PHY-Link interface data signals.
Power supply.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Power supply.
Power supply.
Ground.
Power-up reset external condensor pin.
Analog power supply.
Analog ground.
Analog power supply.
Crystal connection. Crystal oscillator connecting pins.
Crystal connection. Crystal oscillator connecting pins.
Analog ground.
Analog ground.
Analog ground.
Analog power supply.
External loop filter connection pin.
External loop filter connection pin.
Analog ground.
External base resistance connection pin.
External base resistance connection pin.
Cable power status detection pin.
Analog ground.
Analog power supply.
Cable bias output pins.
Arbitration / speed signal / data output; arbitration / strobe input. Reverse-phase I/O pins.
Arbitration / speed signal / data output; arbitration / strobe input. Reverse-phase I/O pins.
Arbitration / speed signal / data output; arbitration / strobe input. Standard-phase I/O pins.
Arbitration / strobe output; arbitration / speed signal / data input. Reverse-phase I/O pins.
Arbitration / speed signal / data output; arbitration / strobe input. Reverse-phase I/O pins.
(Connected to ground.)
Arbitration / speed signal / data output; arbitration / strobe input. Reverse-phase I/O pins.
(Connected to ground.)
Arbitration / speed signal / data output; arbitration / strobe input. Standard-phase I/O pins.
• IC701 CXD1945R PHY, I LINK I/F(MAIN BOARD)
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