Sony MDS-LSA1 Service Manual ▷ View online
61
Function
Pin No.
Pin Name
I/O
48
49
50, 51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
D1
D0
D2, D3
MVCI
ASYO
ASYI
AVDD
BIAS
RFI
AVSS
PCO
FILI
FILO
CLTV
PEAK
BOTM
ABCD
FE
AUX1
VC
ADIO
AVDD
ADRT
ADRB
AVSS
SE
TE
DCHG
APC
ADFG
F0CNT
XLRF
CKRF
DTRF
APCREF
TEST0
TRDR
Data input/output for DRAM
Clock input from an external VCO (Fixed at “L”)
Playback EFM duplex signal output
Playback EFM comparator slice level input
+3V power supply (Analog)
Playback EFM comparator bias current input
Playback EFM RF signal input
Ground (Analog)
Phase comparison output for the recording/playback EFM master PLL
Filter input for the recording/playback EFM master PLL
Filter output for the recording/playback EFM master PLL
Internal VCO control voltage input for the recording/playback EFM master PLL
Light amount signal peak hold input from the CXA2523AR
Light amount signal bottom hold input from the CXA2523AR
Light amount signal input from the CXA2523AR
Focus error signal input from the CXA2523AR
Auxiliary A/D input
Middle point voltage (+1.5V) input from the CXA2523AR
Monitor output of the A/D converter input signal (Not used)
+3V power supply (Analog)
A/D converter operational range upper limit voltage input (Fixed at “H”)
A/D converter operational range lower limit voltage input (Fixed at “L”)
Ground (Analog)
Sled error signal input from the CXA2523AR
Tracking error signal input from the CXA2523AR
Connected to +3V power supply
Error signal input for the laser digital APC (Fixed at “L”)
ADIP duplex FM signal input from the CXA2523AR (22.05 ± 1 kHz)
Filter f
0
control output to the CXA2523AR
Control latch output to the CXA2523AR
Control clock output to the CXA2523AR
Control data output to the CXA2523AR
Reference PWM output for the laser APC
PWM output for the laser digital APC (Not used)
Tracking servo drive PWM output (–)
I/O
I/O
I/O
I (S)
O
I (A)
—
I (A)
I (A)
—
O (3)
I (A)
O (A)
I (A)
I (A)
I (A)
I (A)
I (A)
I (A)
I (A)
O (A)
—
I (A)
I (A)
—
I (A)
I (A)
I (A)
I (A)
I (S)
O
O
O
O
O
O
O
• Abbreviation
EFM: Eight to Fourteen Modulation
PLL : Phase Locked Loop
VCO: Voltage Controlled Oscillator
PLL : Phase Locked Loop
VCO: Voltage Controlled Oscillator
62
Function
Pin No.
Pin Name
I/O
86
87
88
89
90
91
92
93
94
95
96 to 98
99
100
TFDR
DVDD
FFDR
FRDR
FS4
SRDR
SFDR
SPRD
SPFD
FGIN
TEST1 to TEST3
DVSS
EFMO
O
—
O
O
O
O
O
O
O
I (S)
I
—
O
Tracking servo drive PWM output (+)
+3V power supply (Digital)
Focus servo drive PWM output (+)
Focus servo drive PWM output (–)
176.4 kHz clock signal output (X’tal) (Not used)
Sled servo drive PWM output (–)
Sled servo drive PWM output (+)
Spindle servo drive PWM output (–)
Spindle servo drive PWM output (+)
Test input (Fixed at “L”)
Ground (Digital)
EFM output when recording
• Abbreviation
EFM: Eight to Fourteen Modulation
63
1
DATA(FL)
O
Serial data signal output to the display driver.
2
CLK(FL)
O
Serial clock signal output to the display driver. L: Active
3
C1ERROR
I
C1 error input. (Fixed at L)
4
RMC/ERROR
I
Remote control input./AD error detect.
5
DQSY (3202)
I
Digital in sync input from the CXD3202AR.
6 to 10
NC
—
Not used.
11
LD-LOW
O
Loading motor voltage control output L: High voltage H: Low voltage
12
LDIN
I
Loading motor control input. H: IN
13
LDOUT
O
Loading motor control output. H: OUT
14
MOD
O
Laser modulation switching signal output. L: OFF H: ON
15
BYTE
I
Data bus changed input. (Connected to ground.)
16
CNVSS
—
Ground.
17
X-CIN
I
Not used.
18
X-COUT
O
Not used.
19
RESET
I
System rest input. L : ON
20
XOUT
O
Main clock output. (10MHz)
21
VSS
—
Ground.
22
XIN
I
Main clock input. (10MHz)
23
VCC0
—
Power supply. (+3.3V)
24
NMI
I
Fixed at H. (Pull-up)
25
DQSY (MDM/INT2)
I
Digital in sync input. (Record system)
26
P.DOWN (INT1)
I
Power down detection input. L: Power down
27
SQSY (ATSY)
I
ADIP (MO) sync or subcode Q (PIT) sync input from CXD2662R.(Playback system)
28
NC
—
Not used.
29
LDON
O
Laser ON/OFF control output. H: Laser ON
30
LIMIT-IN
I
Detection input from the limit switch. L: Sled limit-In H: Sled limit-Out
31
A1 OUT
O
A1 Control output.
32
XINIT
I
Interrupt status input from CXD2662R.
33
CNT1 (CLIP WRITE)
O
Clip write signal output.
34
XELT
I
Data latch input for DSP.
35
WR PWR
O
Write power ON/OFF output. L: OFF H: ON
36
NC
—
Not used.
37
NC
—
Not used.
38
SWDT
O
Writing data signal output to the serial bus.
39
VCC1
—
Power supply. (+3.3V)
40
SRDT
I
Reading data signal input from the serial bus.
41
VSS1
—
Ground.
42
SCLK (DSP/ADDA)
O
Clock signal output to the serial bus.
43
RECP-SW
I
Detection signal input from the recording position detection switch. L: REC
44
TX0 (CLIP DATA)
O
CLIP serial data output.
45
RX0 (CLIP DATA)
I
CLIP serial data input.
46
CLK0 (CLIP CLK)
O
CLIP serial clock output.
47
DIG-RST
O
Digital rest signal output to the CXD2662R and motor driver. L: Reset
48
SENS
I
Internal status (SENSE) input from the CXD2662R.
49
PLAY-SW
I
Detection signal input from the playback position detection switch. L: PLAY
50
XLATCH
O
Latch signal output to the serial bus.
51
OUT-SW
I
Detection signal input from the loading out detection switch.
52
RDY
I
Fixed at H. (Pull-up)
53
ALE/RAS
O
Microprocessor mode output. (Not used.)
54
HOLD
I
Fixed at H. (Pull-up)
55
HLDA
O
Microprocessor mode output. (Not used.)
56
MNT2 (XBUSY)
I
In the state of executive command from the CXD2662R
57
VSS2
—
Ground.
Function
Pin Name
Pin No.
I/O
• IC501 M30805SGP SYSTEM CONTROL (MAIN BOARD)
64
58
MNT1 (SHCK)
I
Track jump signal input from the CXD2662R
59
VCC2
—
Power supply. (+3.3V)
60
EEP-WP
O
EEP-ROM write protect signal output. L: write possibility
61
SDA (EEP)
I/O
Data signal input/output pin with the EEP-ROM.
62
BCLK
O
Not used.
63
XRD
O
Read signal output.
64
BHE
O
Not used.
65
XWR
O
Write signal output.
66
SCL (EEP)
O
Clock signal output to the EEP-ROM.
67
REFLECT-SW
I
Disk reflection rate detection input from the reflect detection switch. H: Disk with low reflection rate
68
PROTECT-SW
I
Recording-protection claw detection input from the protection detection switch. H: Protect
69
CS0 (F-ROM)
O
Chip select signal output to the Flash ROM.
70
CS1 (S-RAM)
O
Not used.
71
CS2
O
72
A20
O
Address bus signal output to Flash ROM.
73
A19
O
Address bus signal output to Flash ROM.
74
VCC
—
Power supply. (+3.3V)
75
A18
O
Address bus signal output to Flash ROM.
76
VSS
—
Ground
77 to 85
A17 to A9
O
Address bus signal output to Flash ROM.
86 to 89
NC
O
Not used.
90
WP (FLASH)
O
Write protect signal to the Flash ROM.
91
VCC4
—
Power supply. (+3.3V)
92
A8
O
Address bus signal output to Flash ROM.
93
VCC4
—
Power supply. (+3.3V)
94 to 101
A7 to A0
O
Address bus signal output to Flash ROM.
102 to 113
D15 to D4
I/O
Data bus signal input/output to the Flash ROM.
114
NC
—
Not used.
115
NC
—
Not used.
116
NC
—
Not used.
117
TPBIAS
O
Bias on signal output.
118
1394RESET
O
Reset signal output for IEEE1394
119 to 122
D3 to D0
I/O
Data bus signal input/output to the Flash ROM.
123
LED DATA
O
Serial parallel data output for LED.
124
RCLK
O
Serial parallel clock output for LED.
125
CNT2 (CLIP READ)
O
Clip read signal output.
126
SRCK
O
Serial parallel latch output for LED.
127
RST (CLIP)
O
Clip reset signal output.
128
FLCS
O
Chip select signal output to the display driver.
129
CNT3 (RAW AUDIO)
O
RALU audio control signal output.
130
VSS
—
Ground.
131
STB
O
Strobe signal output to the power supply circuit. H: Power supply ON: L: standby
132
VCC
—
Power supply. (+3.3V)
133
OP-LEVEL
I
Optical Pick-up voltage (current) detect signal input.
134
NC
I
Not used.
135 to 138
NC
I
Not used.
139
KEY 1
I
Key input pin (A/D input)
140
AVSS
—
Ground. (Analog)
141
KEY0
I
A/D reference voltage.
142
VREF
—
Power supply. (+3.3V)
143
AVCC
—
Power supply. (+3.3V)
144
NC
I
Not used.
Function
Pin Name
Pin No.
I/O
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