Sony MDS-JB920 Service Manual ▷ View online
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•
BD BOARD IC121 CXD2654R
Pin No.
Pin Name
I/O
Function
1
MNT0 (FOK)
O
Focus OK signal output to the system controller (IC800)
“H” is output when focus is on (“L”: NG)
“H” is output when focus is on (“L”: NG)
2
MNT1 (SHOCK)
O
Track jump detection signal output to the system controller (IC800)
3
MNT2 (XBUSY)
O
Busy monitor signal output to the system controller (IC800)
4
MNT3 (SLOCK)
O
Spindle servo lock status monitor signal output to the system controller (IC800)
5
SWDT
I
Writing serial data signal input from the system controller (IC800)
6
SCLK
I (S)
Serial data transfer clock signal input from the system controller (IC800)
7
XLAT
I (S)
Serial data latch pulse signal input from the system controller (IC800)
8
SRDT
O (3)
Reading serial data signal output to the system controller (IC800)
9
SENS
O (3)
Internal status (SENSE) output to the system controller (IC800)
10
XRST
I (S)
Reset signal input from the system controller (IC800) “L”: reset
11
SQSY
O
Subcode Q sync (SCOR) output to the system controller (IC800)
“L” is output every 13.3 msec Almost all, “H” is output
“L” is output every 13.3 msec Almost all, “H” is output
12
DQSY
O
Digital In U-bit CD format subcode Q sync (SCOR) output to the system controller (IC800)
“L” is output every 13.3 msec Almost all, “H” is output
“L” is output every 13.3 msec Almost all, “H” is output
13
RECP
I
Laser power selection signal input from the system controller (IC800)
“H”: recording mode, “L”: playback mode
“H”: recording mode, “L”: playback mode
14
XINT
O
Interrupt status output to the system controller (IC800)
15
TX
I
Recording data output enable signal input from the system controller (IC800)
Writing data transmission timing input (Also serves as the magnetic head on/off output)
Writing data transmission timing input (Also serves as the magnetic head on/off output)
16
OSCI
I
System clock signal (512Fs=22.5792 MHz) input from the D/A converter (IC200)
17
OSCO
O
System clock signal (512Fs=22.5792 MHz) output terminal Not used (open)
18
XTSL
I
Input terminal for the system clock frequency setting
“L”: 45.1584 MHz, “H”: 22.5792 MHz (fixed at “H” in this set)
“L”: 45.1584 MHz, “H”: 22.5792 MHz (fixed at “H” in this set)
19
DIN0
I
Digital audio signal input terminal when recording mode (for digital optical in/digital coaxial in)
20
DIN1
I
Digital audio signal input terminal when recording mode Not used (fixed at “L”)
21
DOUT
O
Digital audio signal output terminal when playback mode (for digital optical out/digital coaxial
out)
out)
22
DATAI
I
Serial data input terminal Not used (fixed at “L”)
23
LRCKI
I
L/R sampling clock signal (44.1 kHz) input terminal Not used (fixed at “L”)
24
XBCKI
I
Bit clock signal (2.8224 MHz) input terminal Not used (fixed at “L”)
25
ADDT
I
Recording data input from the A/D converter (IC100)
26
DADT
O
Playback data output to the D/A converter (IC200)
27
LRCK
O
L/R sampling clock signal (44.1 kHz) output to the A/D converter (IC100) and D/A converter
(IC200)
(IC200)
28
XBCK
O
Bit clock signal (2.8224 MHz) output to the A/D converter (IC100) and D/A converter (IC200)
29
FS256
O
Clock signal (11.2896 MHz) output terminal Not used (open)
30
DVDD
—
Power supply terminal (+3.3V) (digital system)
31 to 34
A03 to A00
O
Address signal output to the D-RAM (IC124)
35
A10
O
Address signal output to the external D-RAM Not used (open)
36 to 40
A04 to A08
O
Address signal output to the D-RAM (IC124)
41
A11
O
Address signal output to the external D-RAM Not used (open)
42
DVSS
—
Ground terminal (digital system)
43
XOE
O
Output enable signal output to the D-RAM (IC124) “L” active
44
XCAS
O
Column address strobe signal output to the D-RAM (IC124) “L” active
* I (S) stands for schmitt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O.
(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR, EFM/ACIRC ENCODER/DECODER,
SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER)
SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER)
– 34 –
Pin No.
Pin Name
I/O
Function
45
A09
O
Address signal output to the D-RAM (IC124)
46
XRAS
O
Row address strobe signal output to the D-RAM (IC124) “L” active
47
XWE
O
Write enable signal output to the D-RAM (IC124) “L” active
48
D1
I/O
49
D0
I/O
50
D2
I/O
51
D3
I/O
52
MVCI
I (S)
Digital in PLL oscillation input from the external VCO Not used (fixed at “L”)
53
ASYO
O
Playback EFM full-swing output terminal
54
ASYI
I (A)
Playback EFM asymmetry comparator voltage input terminal
55
AVDD
—
Power supply terminal (+3.3V) (analog system)
56
BIAS
I (A)
Playback EFM asymmetry circuit constant current input terminal
57
RFI
I (A)
Playback EFM RF signal input from the CXA2523AR (IC101)
58
AVSS
—
Ground terminal (analog system)
59
PCO
O (3)
Phase comparison output for master clock of the recording/playback EFM master PLL
60
FILI
I (A)
Filter input for master clock of the recording/playback master PLL
61
FILO
O (A)
Filter output for master clock of the recording/playback master PLL
62
CLTV
I (A)
Internal VCO control voltage input of the recording/playback master PLL
63
PEAK
I (A)
Light amount signal (RF/ABCD) peak hold input from the CXA2523AR (IC101)
64
BOTM
I (A)
Light amount signal (RF/ABCD) bottom hold input from the CXA2523AR (IC101)
65
ABCD
I (A)
Light amount signal (ABCD) input from the CXA2523AR (IC101)
66
FE
I (A)
Focus error signal input from the CXA2523AR (IC101)
67
AUX1
I (A)
Auxiliary signal (I
3
signal/temperature signal) input from the CXA2523AR (IC101)
68
VC
I (A)
Middle point voltage (+1.65V) input from the CXA2523AR (IC101)
69
ADIO
O (A)
Monitor output of the A/D converter input signal Not used (open)
70
AVDD
—
Power supply terminal (+3.3V) (analog system)
71
ADRT
I (A)
A/D converter operational range upper limit voltage input terminal (fixed at “H” in this set)
72
ADRB
I (A)
A/D converter operational range lower limit voltage input terminal (fixed at “L” in this set)
73
AVSS
—
Ground terminal (analog system)
74
SE
I (A)
Sled error signal input from the CXA2523AR (IC101)
75
TE
I (A)
Tracking error signal input from the CXA2523AR (IC101)
76
DCHG
I (A)
Connected to the +3.3V power supply
77
APC
I (A)
Error signal input for the laser automatic power control Not used (fixed at “H”)
78
ADFG
I (S)
ADIP duplex FM signal (22.05 kHz
±
1 kHz) input from the CXA2523AR (IC101)
79
F0CNT
O
Filter f0 control signal output to the CXA2523AR (IC101)
80
XLRF
O
Serial data latch pulse signal output to the CXA2523AR (IC101)
81
CKRF
O
Serial data transfer clock signal output to the CXA2523AR (IC101)
82
DTRF
O
Writing serial data output to the CXA2523AR (IC101)
83
APCREF
O
Control signal output to the reference voltage generator circuit for the laser automatic power
control
control
84
LDDR
O
PWM signal output for the laser automatic power control Not used (open)
85
TRDR
O
Tracking servo drive PWM signal (–) output to the BH6511FS (IC152)
86
TFDR
O
Tracking servo drive PWM signal (+) output to the BH6511FS (IC152)
87
DVDD
—
Power supply terminal (+3.3V) (digital system)
88
FFDR
O
Focus servo drive PWM signal (+) output to the BH6511FS (IC152)
89
FRDR
O
Focus servo drive PWM signal (–) output to the BH6511FS (IC152)
90
FS4
O
Clock signal (176.4 kHz) output terminal (X’tal system) Not used (open)
* I (S) stands for schmitt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O.
Two-way data bus with the D-RAM (IC124)
– 35 –
Pin No.
Pin Name
I/O
Function
91
SRDR
O
Sled servo drive PWM signal (–) output to the BH6511FS (IC152)
92
SFDR
O
Sled servo drive PWM signal (+) output to the BH6511FS (IC152)
93
SPRD
O
Spindle servo drive PWM signal (–) output to the BH6511FS (IC152)
94
SPFD
O
Spindle servo drive PWM signal (+) output to the BH6511FS (IC152)
95
FGIN
I (S)
96
TEST1
I
97
TEST2
I
98
TEST3
I
99
DVSS
—
Ground terminal (digital system)
100
EFMO
O
EFM signal output terminal when recording mode
* I (S) stands for schmitt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O.
Input terminal for the test (fixed at “L”)
– 36 –
•
MAIN BOARD IC100 CXD8607N (A/D CONVERTER)
Pin No.
Pin Name
I/O
Function
1
INRP
I
R-ch analog signal (–) input terminal
2
INRM
I
R-ch analog signal (+) input terminal
3
REFI
I
Reference voltage (+3.3V) input terminal (for A/D converter section)
4
AVDD
—
Power supply terminal (+5V) (for A/D converter section, analog system)
5
AVSS
—
Ground terminal (for A/D converter section, analog system)
6
APD
I
Power down detection input of the A/D converter section (for analog section) “L”: power down
7
NU
—
Not used (open)
8
NU
—
Not used (open)
9
TEST1
I
Input terminal for the test (fixed at “L”)
10
LRCK1
I
L/R sampling clock signal (44.1 kHz) input from the CXD2654R (IC121) (for A/D converter
section)
section)
11
BCK1
I
Bit clock signal (2.8224 MHz) input from the CXD2654R (IC121) (for A/D converter section)
12
ADDT
O
Recording data output to the CXD2654R (IC121)
13
V35A
—
Power supply terminal (+3.3V) (for analog system)
14
VSS1
—
Ground terminal (for A/D converter section, digital system)
15
MCKI
I
Master clock (256Fs=11.2896 MHz) input of the A/D converter section
16
DPD
I
Reset signal input from the system controller (IC800) Reset signal is used as a detection signal
of power down to A/D converter section (digital section) “L”: reset (power down)
of power down to A/D converter section (digital section) “L”: reset (power down)
17
VSS2
—
Ground terminal (for D/A converter section, digital system)
18
RES
I
Reset signal input terminal Reset signal is used as a initialize signal to D/A converter section
“L”: reset (initialize) Not used D/A converter section in this set
“L”: reset (initialize) Not used D/A converter section in this set
19
MODE
I
Writing data input terminal Not used (fixed at “L”)
20
SHIFT
I
Serial clock signal input terminal Not used (fixed at “L”)
21
XLATCH
I
Serial data latch pulse signal input terminal Not used (fixed at “L”)
22
256CK
O
256Fs (11.2896 MHz) clock signal output terminal Not used (open)
23
V35D
—
Power supply terminal (+3.3V) (for digital system) Not used (open)
24
VSS2
—
Ground terminal (for D/A converter section, digital system)
25
512FS
O
512Fs (22.5792 MHz) clock signal output terminal Not used (pull down)
26
BCK2
I
Bit clock signal (2.8224 MHz) input terminal (for D/A converter section)
Not used (fixed at “L”)
Not used (fixed at “L”)
27
DADT
I
Playback data input terminal Not used (fixed at “L”)
28
LRCK2
I
L/R sampling clock signal (44.1 kHz) input terminal (for D/A converter section)
Not used (fixed at “L”)
Not used (fixed at “L”)
29
VDD2
—
Power supply terminal (+5V) (for D/A converter section, digital system)
Not used (fixed at “L”)
Not used (fixed at “L”)
30
R1
O
R-ch PLM signal 1 output terminal Not used (open)
31
AVDDR
—
Power supply terminal (+5V) (for R-ch side D/A converter section, analog system)
Not used (fixed at “L”)
Not used (fixed at “L”)
32
R2
O
R-ch PLM signal 2 output terminal Not used (open)
33
AVSSR
—
Ground terminal (for R-ch side D/A converter section, analog system)
34
XVDD
—
Power supply terminal (+5V) (for X’tal system) Not used (open)
35
XOUT
O
System clock output terminal (22 MHz) Not used (open)
36
XIN
I
System clock input terminal (22 MHz) Not used (fixed at “L”)
37
XVSS
—
Ground terminal (for X’tal system)
38
AVSSL
—
Ground terminal (for L-ch side D/A converter section, analog system)
39
L2
O
L-ch PLM signal 2 output terminal Not used (open)
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