Sony MDS-JA50ES Service Manual ▷ View online
— 86 —
Function
Pin No.
Pin Name
I/O
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
WFCK
GTOP
GFS
XPLCK
EFMO
RAOF
MVCI
TEST2
DIPD
DVSS
DICV
DIFI
DIFO
AVDD
ASYO
ASYI
BIAS
RFI
AVSS
CLTV
PCO
FILI
FILO
PEAK
BOTM
ABCD
FE
AUX1
VC
ADIO
TEST3
AVDD
ADRT
ADRB
AVSS
SE
TE
AUX2
DCHG
APC
O
O
O
O
O
O
I
I
O (3)
—
I (A)
I (A)
O (A)
—
O
I (A)
I (A)
I (A)
—
I (A)
O (3)
I (A)
O (3)
I (A)
I (A)
I (A)
I (A)
I (A)
I (A)
O (A)
I (A)
—
I (A)
I (A)
—
I (A)
I (A)
I (A)
I (A)
I (A)
WFCK clock (7.35 kHz) signal output
(Playback: EFM decoder PLL
Recording: EFM encoder PLL)
“H”: Opens playback EFM frame sync protection window
“H”: Playback EFM sync and interpolation protection timing match
EFM decoder PLL clock output (98 fs=4.3218 MHz)
Falling edge and EFM signal edge match
EFM signal output (Recording)
Internal RAM overflow detection signal output (decoder monitor output)
Outputs “H” when the disc rotation exceeds ±4F jitter margin during playback
Digital-in PLL oscillation input (Not used) (Fixed at “L”)
Test pin (Fixed at “L”)
Digital-in PLL phase comparison output
Internal VCO: (Frequency: Low
n “H”) External VCO: (Frequency: Low n “L”)
Ground (Digital)
Digital-in PLL internal VCO control voltage input
Filter input when digital-in PLL internal VCO is used
Filter output when digital-in PLL internal VCO is used (Not used)
Power supply (+5V) (Analog )
Playback EFM full-swing output (L=VSS, H=VDD)
Playback EFM asymmetry comparate voltage input
Playback EFM asymmetry circuit constant current input
Inputs playback EFM RF signal from RF amplifier
Ground (Analog )
Decoder PLL master clock PLL VCO control voltage input
Decoder PLL master clock PLL phase comparison output
Decoder PLL master clock PLL filter input
Decoder PLL master clock PLL filter output
Inputs peak hold signal for light amount signal from RF amplifier
Inputs bottom hold signal for light amount signal from RF amplifier
Light amount signal from RF amplifier
Input of focus error signal from RF amplifier
Input of auxiliary signal from RF amplifier
Input of middle point voltage (+2.5V) from RF amplifier
A/D converter input signal monitor output
Test input (Fixed at “L”)
Power supply (+5V) (Analog)
A/D converter operation range upper limit voltage input (Fixed at “H”)
A/D converter operation range lower limit voltage input (Fixed at “L”)
Ground (Analog)
Input of sled error signal from RF amplifier
Input of tracking error signal from RF amplifier
Auxiliary input pin 2 (Fixed at “L”)
Connected to ground
Laser APC input (Fixed at “L”)
• Abbreviation
EFM : Eight to Fourteen Modulation
PLL : Phase Locked Loop
PLL : Phase Locked Loop
— 87 —
Function
Pin No.
Pin Name
I/O
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
TEST1
ADFG
TS25
LDDR
TRDR
TFDR
FFDR
DVDD
FRDR
FS4
SRDR
SFDR
SPRD
SPFD
DCLO
DCLI
XDCL
OFTRK
COUT
DVSS
I
I
I
O
O
O
O
—
O
O
O
O
O
O
O
I
O
O
O
—
Test pin (Fixed at “L”)
Input of ADIP dual FM signal from RF amplifier (22.05 kHz ±1 kHz)
(TTL Schmidt input)
Test pin (Fixed at “L”)
Laser APC signal output
Tracking servo drive signal output (–)
Tracking servo drive signal output (+)
Focus servo drive signal output (+)
Power supply (+5V) (Digital)
Focus servo drive signal output (–)
176.4 kHz clock signal output (MCLK) (Not used)
Sled servo drive signal output (–)
Sled servo drive signal output (+)
Spindle servo drive signal output (–)
Spindle servo drive signal output (+)
Not used normally
Not used normally (Fixed at “H”)
Not used normally
Off track signal output (Not used)
Traverse count signal output (Not used)
Ground (Digital)
* (3) of I/O is 3-state output, (A) is analog output.
— 88 —
Pin No.
Pin Name
I/O
Function
• IC202 System Controller (M30610EC-1086FP)/DIG board
1, 2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21, 22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
—
I
I
I
I
—
I
—
I
O
I
O
—
I
—
I
—
I
I
—
I
O
O
O
O
O
O
O
O
I
O
—
O
—
O
O
—
O
O
O
I
O
—
JOG0
JOG1
SQSY
REMOCON
—
BYTE
CNVSS
XIN-T
XOUT-T
SYSTEM-RST
XOUT
GND
XIN
+5V
MNI
—
POWER DOWN
DQSY
—
XINT
04LAT
62RST
95RST
95LAT
ADRST
ADLAT
XLATCH
SWDT
SRDT
SCLK
—
FLDATA
—
FLCLK
FLCS
—
COAX/XOPT
OPT1/XOPT2
DIN/XMD
EROR
SRCRST
Not used
AMS jog signal input
ATP address sync or sub code Q sync (SCOR) input from CXD2535CR
“L” is input every 13.3 msec
Mainly “H”
Remote control signal interruption input
Not used
Data bus switching signal input
“L”:Single chip mode (Fixed at “L”)
Ground
Sub clock input (37.768 kHz)
Sub clock output (32.768 kHz)
System reset input “L”:Reset
Main clock output (10 MHz)
Ground
Main clock input (10 MHz)
Power supply (+5V)
Not used
Power down detection signal input
“L”:Power down
Digital-in U-bit CD format sub code Q sync (SCOR) input from CXD2535CR
“L” is input every 13.3 msec
Mainly “H”
Not used
Interruption status input from ATRAC encoder/decoder
Data read signal output to sampling rate converter, digital filter
“L”:Active
Reset signal output to D/A converter
“L”:Reset
Reset signal output to CXD8595Q
“L”:Reset
Transmission data latch signal output to CXD8595Q
Reset signal output to A/D converter
“H”:Reset
Latch signal output to A/D converter
Serial data latch signal output
Write data signal input to serial bus
Read data signal input from serial bus
Clock signal output to serial bus
Not used
Transmission data clock output to FL driver
Not used
Transmission data clock output to FL driver
Transmission data chip select output to FL driver
Not used
Digital-in select signal output
“L”:Optical input, “H”:Coaxial input
Digital-in select signal output
“L”:OPT2, “H”:OPT1
Digital-out select signal output
“L”:MD, “H”:Digital in through
Digital-in error signal input
Reset signal output to sampling rate converter, digital filter
“L”:Reset
• Abbreviation
FL : Fluorescent indicator tube
— 89 —
0.5S
2S
Function
Pin No.
Pin Name
I/O
45
46 to 48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
SRC TEST
—
DAMUTE
STB
OUTSW
INSW
—
LDIN
LDOUT
HUP
HDWN
37RST
HUPS
HDOWNS
REC/PB
VCC
—
VSS
—
MOD
SCTX
FG
FOK
SHCK
WRPWR
DIG-RST
—
SDA
SCL
SENS
PROTECT
REFLECT
LDON
LIMIT-IN
O
—
O
O
I
I
—
O
O
O
O
O
I
I
O
—
—
—
—
O
O
I
I
I
O
O
—
I/O
O
I
I
I
O
I
The second reset signal output from sampling rate converter
Not used
D/A line mute output
“L”:Active
Strobe signal output to power supply circuit
When power is ON:“H”, When standby:“L”
Detection input from loading out detection switch
Detection input from loading in detection switch
Not used
Loading motor control output
Magnetic head up/down control output
Reset signal output to ATRAC encoder/decoder
“L”:Reset
Detection input from magnetic head up detection switch
Detection input from magnetic head down detection switch
Recording/playback selection signal output to CXD2535CR
When recording:“H”, when playing back:“L”
Power supply (+5V)
Not used
Ground
Not used
Laser modulation switching signal output
During playback power: “L”, During stop:“H”
During recording power:
Write data transmission timing output to ATRAC encoder/decoder
Used also as magnetic head ON/OFF output
FG detection signal output from spindle motor driver
FOK signal input from CXD2535CR
“H” is input when focus is set
Track jump detection signal input from CXD2535CR
Laser power switching signal output to optical pick-up and CXD2535CR
Digital reset signal output
Not used
Input/output of data signal with EEPROM
Clock signal output to EEPROM
Internal status (SENSE) input from CXD2535CR
Recording prevention tab detection input from protect detection switch
When protect is ON:“H”
Disc reflection rate detection input from reflect detection switch
When low reflection rate disc is used:“H”
Laser ON/OFF control output
“H”:Laser ON
Detection input from limit-in switch
When sled limit in:“L”
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