Sony MDS-JA50ES Service Manual ▷ View online
— 82 —
IC502 CXD2562Q-CS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
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45
46
56
55
54
53
52
51 50 49 48 47
57
58
59
60
61
62
63
64
S/P
TIMING CIRCUIT
INTERPOLATER
INTERPOLATER
THIRD ORDER
NOISE SHAPER
THIRD ORDER
NOISE SHAPER
PLM
PLM
CLOCK
GENERATOR
SYNC
COEF
SPLM
18/20
DVDDR
VSUB (D) R
VSUB (CHIP) R
VDD2
VDD
R1 (–)
VSS
R1 (+)
VSS2
VSS2
L1 (+)
VSS
L1 (–)
VDD
VDD2
VSUB (CHIP) L
VSUB (D) L
DVDDL
TEST3
TEST2
TEST1
DATAOUT
ON/OFF
VSS2
L2 (+)
VSS
L2 (–)
VDD
VDD2
VSUB (A) L
XVDD
XOUT
XIN
XVSS
XVSS
VSUB (A) R
VDD2
VDD
R2 (–)
VSS
R2 (+)
VSS2
DRI
LRCKI
MUTEL
MUTER
INIT
DVSSL
DVSSR
512FSO
BCKI
DLI
DRO
LRCKO
INAF
DINIT
128FS
DPO/BCKO
DM2/SDRO
DM1/SDLO
DLO
IC504, 505 CXA8042AS
IC701 M66004M8FP
INDICATION
CODE
RESISTOR
(8BIT x 16)
DECODER
(35BIT x 16)
DECODER
(35BIT x 16)
CODE/COMMAND
CONTROL
CIRCUIT
INDICATION
CONTROL
RESISTOR
INDICATION
CONTROLLER
DIGITAL
OUTPUT
CIRCUIT
OUTPUT
CIRCUIT
CODE
WRITE
SERIAL
RECEIVE
CIRCUIT
OUTPUT
PORT
(2BIT)
CLOCK
GENERATOR
CIRCUIT
RAM WRITE
CODE SELECT
DIG12
|
DIG15
V
CC
2
SEG0
|
SEG26
V
SS
XIN
XOUT
V
CC
1
RES
DIG11
|
DIG0
CS
CLK
DATA
SEG35
|
SEG27
P1
P0
14
15
16
17
18
19
20
21
22
23
|
31
13
1
|
12
SEGMENT OUTPUT CIRCUIT
59
|
33
60
32
VP
64
|
61
1
2
3
4
4
5
6
7
8
9
10
11
12
13
14
13
14
28
27
26
25
25
24
23
22
21
20
19
18
17
16
15
15
SWITCHING
CIRCUIT
CONSTANT
CURRENT
CIRCUIT
REFERENCE
VOLTAGE
CIRCUIT
CONTROL
CIRCUIT
I01+
IN2–
IN2+
NC
IN1+
IN1–
IN1–
NC
C4
C4
C3
GND2
GND2
VEE2
VEE1
C6
C5
CIREF
I02–
NC
I01–
I02+
NC
VCC2
C2
C1
C1
VCC1
VREF
VCNT
GND1
RIREF
— 83 —
IC901 M62005L
IC902 LA5602
1
2
3
4
5
7
6
V IN
EN
GND
CDEL
CN
RES
V OUT
REFERENCE
VOLTAGE
OVER HEAT
PROTECTION
OVER CURRENT
LIMITTER
ON/OFF
RESET
GEN
ERROR
AMP
IC906 SN74HC04ANS-E20
14
13
12
11
10
9
8
1
2
3
4
5
6
7
VCC
GND
IC908 M5293L
2
5
5k
+
–
27k
OVERCURRENT
LIMITTER
OVERHEAT
PROTECTION
REFERENCE
VOLTAGE
GND
ON/OFF
IN
REFERENCE
VOLTAGE
VOLTAGE
OUT
3
4
1
1
2
3
4
5
VCC
Cd
RESET
INT
GND
+
–
+
–
RESET
SIGNAL
GENERATOR
INTERRUPT
SIGNAL
GENERATOR
— 84 —
6-21. IC PIN FUNCTIONS
• IC101 RF Amplifier (CXA1981AR)/BD board
Pin No.
Pin Name
I/O
Function
VC
A to F
FI
FO
PD
APCREF
TEMPI
GND
AAPC
DAPC
TEMPR
XRST
SWDT
SCLK
XLAT
VREF
TENV
THLD
VCC
TFIL
TE
TLB
CSLED
SE
ADFM
ADIN
ADAGC
ADFG
AUX
FE
FLB
ABCD
BOTM
PEAK
RFAGC
RF
ISET
AGCT
RFO
MORFI
MORFO
I, J
O
I
I
O
I
I
I
—
O
O
O
I
I
I
I
O
O
I
—
I
O
I
I
O
O
I
I
O
O
O
I
O
O
O
I
O
I
I
O
I
O
I
Middle point voltage (+2.5V) generation output
Input of signal from optical pick-up detector
F operation amplifier input
F operation amplifier output
Front monitor
Connected to photo diode
Input for setting laser power
Temperature sensor connection pin
Ground
APC LD amplifier output
Digital APC output (Not used)
Temperature sensor reference voltage output
Input of reset signal from system controller
Reset: “L”
Input of write data signal from system controller
Input of clock signal from system controller
Input of latch signal from system controller
Reference voltage output (Not used)
Tracking envelop signal output (Not used)
Track hold capacitor connection pin
Power supply (+5V)
Track hold input (Connected to VC)
Output of tracking error signal to CXD2535CR
Input of add signal to tracking error
Sled error LPF pin
Output of sled error signal to CXD2535CR
ADIP FM signal output
Inputs ADIP FM signal by AC coupling
Connection pin of external capacitor for ADIP AGC
Output of ADIP dual FM signal to CXD2535CR (22.05 kHz±1 kHz)
Output of auxiliary signal to CXD2535CR
Output of focus error signal to CXD2535CR
Focus bias control input (Not used)
Output of light amount signal to CXD2535CR
Output of bottom hold signal of light amount signal to CXD2535CR
Output of peak hold signal of light amount signal to CXD2535CR
Connection pin of RF AGC circuit external capacitor
Output of playback EFM RF signal to CXD2535CR
Internal circuit constant setting pin
22 kHz BPF center frequency (Fixed at “H”)
Inputs RF signal by AC coupling
Output pin of RF signal
Inputs MO RF signal by AC coupling
Output pin of MO RF signal
Input of signal from optical pick-up detector
1
2 to 7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
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40
41
42
43
44
45
46
47, 48
— 85 —
• IC121 Digital Signal Processor, Digital Servo Processor, EFM/ACIRC Encoder/Decoder (CXD2535CR)/BD board
Function
Pin No.
Pin Name
I/O
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
FS256
FOK
DFCT
SHCK
SHCKEN
WRPWR
DIRC
SWDT
SCLK
XLAT
SRDT
SENS
ADSY
SQSY
DQSY
XRST
TEST4
CLVSCK
TEST5
DOUT
DIN
FMCK
ADER
REC
DVSS
DOVF
DODT
DIDT
DTI
DTO
C2PO
BCK
LRCK
XTAO
XTAI
MCLK
XBCK
DVDD
WDCK
RFCK
O
O
O
O
I
I
I
I
I
I
O
O (3)
O
O
O
I
I
O
I
O
I
O
O
I
—
I
I
O
I
O (3)
O
O
O
O
I
O
O
—
O
O
11.2896 MHz clock output (MCLK) (Not used)
Output of FOK signal to system controller
Outputs “H” when focus is set
Outputs defect ON/OFF switching signal to ATRAC encoder/decoder
Outputs track jump detection signal to system controller
Track jump detection enable input (Not used) (Fixed at “H”)
Inputs laser power switching signal from system controller
Disc drive recording/playback switching signal input (Fixed at “H”)
Inputs write data signal from system controller
Inputs serial clock signal from system controller
Inputs serial latch signal from system controller
Outputs read data signal to system controller
Outputs internal status (SENSE) to system controller
ADIP sync signal output (Not used)
Output subcode Q sync (SCOR) to system controller
Outputs “L” every 13.3 msec Outputs “H” at all most mostly
Outputs digital-in U-bit CD format subcode Q sync (SCOR) to system controller
Outputs “L” every 13.3 msec Outputs “H” at all most mostly
Inputs reset signal from system controller
Reset: “L”
Test input (Fixed at “L”)
Not used
Test input (Fixed at “L”)
Digital audio signal output (For optical output)
Digital audio signal input (For optical input) (Not used)
ADIP FM demodulation clock signal output
ADIP CRC flag output
“H”:Error
Input of recording/playback switching signal from system controller
Recording: “H”
Playback: “L”
Ground (Digital)
Digital audio output validity flag input (Fixed at “L”)
Input of 16bit data for digital audio output
Output of 16bit data for digital audio input to ATRAC encoder/decoder
Input of recording audio data signal from ATRAC encoder/decoder
Output of playback audio data signal to ATRAC encoder/decoder
Outputs C2PO signal to ATRAC encoder/decoder (Output indicating data error status)
Playback: C2PO (“H”)
Digital recording: Digital-in-Vflag
Analog recording: “L”
Outputs bit clock signal (2.8224 MHz) (MCLK)
Outputs L/R clock signal (44.1 kHz) (MCLK)
System clock (512 fs=22.5792 MHz) signal output
Input of system clock (512fs=22.5792 MHz) signal input
MCLK clock (22.5792 MHz) signal output (Not used)
Pin 32 (BCK) inversion output (Not used)
Power supply (+5V) (Digital)
WDCK clock (88.2 kHz) signal output (MCLK)
RFCK clock (7.35 kHz) signal output (MCLK)
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