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– 84 –

Pin No.

Pin Name

I/O

Function

45

READY-KEY

I

Ready status input from the CXD2720Q (IC801)

46

XS24-KEY

O

Not used (pull up)

47

RST-37

O

Reset signal output to the ATRAC encoder (IC501) and ATRAC decoder (IC601)    “L”: reset

48

RST-DIG

O

Reset signal output to the CXA1981AR (IC101), CXD2535CR (IC121), MPC17A38VMEL
(IC151), A/D, D/A converter (IC301), digital audio interface receiver (IC401), sampling rate
converter (IC451, 751) and CXD2720Q (IC801)    “L”: reset

49

AMUTE

O

Analog line muting on/off control signal output terminal    “L”: muting on

50

ERROR

I

SRC error detection signal input from the digital audio interface receiver (IC401)    “H”: error

51

STB

O

Strobe control signal output to the power supply circuit    “L”: standby mode, “H”: power on

52

DSEL

O

Selection signal output to the serial data selector (IC154)
“L”: ATRAC decoder (IC601), “H”: ATRAC encoder (IC501)

53

DODT-SEL

O

Selection signal output to the DODT selector (IC153)
“L”: ATRAC encoder (IC501), “H”: CXD2720Q (IC801)

54

AOUT-SEL

O

Selection signal output to the line out selector (IC153)
“L”: ATRAC encoder (IC501), “H”: ATRAC decoder (IC601)

55

LN/OPT-SEL

O

Not used (pull down)

56

RPD0

O

Serial data output to the DSP (IC701)

57

OUT SW

I

Detection input from the disc out switch (S192)    “L”: open position

58

PLAY SW

I

Detection input from the playback position switch (S191)    “L”: playback position

59

REC SW

I

Detection input from the recording position switch (S193)    “L”: recording position

60

LOAD IN

O

61

LOAD OUT

O

62

VCC

—

Power supply terminal (+5V)

63

SDA-BAL

O

Not used (open)

64

VSS

—

Ground terminal

65

REC/PB

O

Recording/playback selection signal output to the CXD2535CR (IC121)
“L”: playback mode, “H”: recording mode

Laser modulation select signal output to the HF module switch circuit

Playback power: “H”, Stop: “L”,

Recording power:

66

MOD

O

67

SCTX

O

Recording data output enable signal output to the ATRAC encoder (IC501), ATRAC decoder
(IC601) and overwrite head driver (IC181)
Writing data transmission timing output (Also serves as the magnetic head on/off output)

68

FG

I

Spindle motor FG detection signal input from the CXD2535CR (IC121)

69

FOK

I

Focus OK signal input from the CXD2535CR (IC121)
“H” is input when focus is on (“L”: NG)

70

SHOCK

I

Track jump detection signal input from the CXD2535CR (IC121)

2 sec

0.5 sec

Loading motor (M191) drive signal output to the motor driver (IC901)
“L” active    *1

*1  Loading motor (M191) control

Mode  

  Terminal

LOAD IN (pin ^º)

“L”

“H”

“L”

“H”

LOAD OUT (pin ^¡)

“H”

“L”

“L”

“H”

LOADING

EJECT

BRAKE

RUN IDLE

– 85 –

Pin No.

Pin Name

I/O

Function

71

WPOWER

O

Laser power select signal output to the CXD2535CR (IC121) and HF module switch circuit
“L”: playback mode, “H”: recording mode

72

SDA-CDSP

I/O

Two-way data bus with the DSP (IC701)

73

SND-CDSP

O

Not used (open)

74

SDA

I/O

Two-way data bus with the EEPROM (IC171)

75

SCL

O

Serial clock signal output to the EEPROM (IC171) and DSP (IC701)

76

SENSE

I

Internal status monitor input from the CXD2535CR (IC121)

77

PROTECT

I

Rec-proof claw detect input from the protect detect switch (S102)    “H”: write protect

78

REFLECT

I

Detection input from the disc reflection rate detect switch (S102)
“L”: high reflection rate disc, “H”: low reflection rate disc

79

LD-ON

O

Laser diode on/off selection signal output to the automatic power control circuit
“H”: laser on

80

LIMIT-IN

I

Detection input from the sled limit-in detect switch (S101)
The optical pick-up is inner position when “L”

81

RVS

O

Playback direction control signal output to the DSP (IC701)    “L”: RVS, “H”: FWD

82

SERIAL OK

O

Communicate information output terminal    “L”: NG, “H”: OK    Not used (pull up)

83

SC TRANSFER

O

Sector transfer information output of the CXD2537R (IC501, IC601)    “H”: transfer
Not used (pull up)

84

—

O

Not used (pull up)

85

SRDT-SEL

O

Selection signal output to the SRDT selector (IC152)
“L”: ATRAC encoder (IC501), “H”: ATRAC decoder (IC601)

86

FACTORY

I

Market/factory mode selection signal input terminal    “L”: market, “H”: factory
Fixed at “L” in this set

87

FAN CONT

O

Fan motor (M801) drive signal output terminal    “L”: motor on, “H”: low speed

88

DESTINATION

I

Setting terminal for the destination    Fixed at “H” in this set

89 to 95

—

O

Not used (pull up)

96

AVSS

—

Ground terminal (for A/D converter)

97

—

O

Not used (pull up)

98

AVREF

I

Reference voltage (+5V) input terminal (for A/D converter)

99

AVCC

—

Power supply terminal (+5V) (for A/D converter)

100

—

O

Not used (pull up)

– 86 –

•

Pin No.

Pin Name

I/O

Function

1

GNDA

—

Ground terminal (for EMI control output buffer)

2

MCS0

O

Chip select signal output terminal    Not used (open)

3 to 5

MA15 to MA13

O

Address signal output terminal    Not used (open)

6

VCCA

—

Power supply terminal (+5V) (for EMI address output buffer and EMI control output buffer)

7

MA12

O

Address signal output terminal    Not used (open)

8

GNDA

—

Ground terminal (for EMI address output buffer)

9

VCCQ

—

Power supply terminal (+5V) (for internal logic)

10

GNDQ

—

Ground terminal (for internal logic)

11, 12

MA11, MA10

O

Address signal output terminal    Not used (open)

13, 14

MA09, MA08

O

Address signal output to the D-RAM (IC702)

15

GNDA

—

Ground terminal (for EMI address output buffer)

16

MA07

O

Address signal output to the D-RAM (IC702)

17

VCCA

—

Power supply terminal (+5V) (for EMI address output buffer and EMI control output buffer)

18 to 20

MA06 to MA04

O

Address signal output to the D-RAM (IC702)

21

GNDA

—

Ground terminal (for EMI address output buffer)

22 to 25

MA03 to MA00

O

Address signal output to the D-RAM (IC702)

26

SCL

I

Serial clock signal input from the system controller (IC101)

27

EXTAL

I

System clock signal input terminal    Bit clock signal input in this set

28

VCCQ

—

Power supply terminal (+5V) (for internal logic)

29

GNDQ

—

Ground terminal (for internal logic)

30

PINIT

I

PLL initialize terminal    Not used (fixed at “L”)

31

GNDP

—

Ground terminal (for PLL system)

32

PCAP

—

Connected to capacitor (for PLL filter)

33

VCCP

—

Power supply terminal (+5V) (for PLL system)

34

GNDS

—

Ground terminal (for SAI, SHI and ONCE output buffer)

35

SDA

I/O

Two-way data bus with the system controller (IC101)

36

RESET

I

System reset signal input from the system controller (IC101)    “L”: reset

37

MODA/IRQA

I

38

MODB/IRQB

I

Mode selection terminal    Fixed at “H” in this set

39

MODC/NMI

I

40

VCCS

—

Power supply terminal (+5V) (for SAI, SHI and ONCE output buffer)

41, 42

HA0, HA2

I

Not used (fixed at “L”)

43

HREQ

I

Not used (fixed at “H”)

44

GNDS

—

Ground terminal (for SAI, SHI and ONCE output buffer)

45

SDO2

O

Enable control signal output to the shift register and latch (IC256, 257)

46

SDO1

O

Serial data output to the shift register and latch (IC256, 257)

47

SDO0

O

Playback serial data output to the CXD8517Q (IC751)

48

VCCS

—

Power supply terminal (+5V) (for SAI, SHI and ONCE output buffer)

49

SCKT

O

Bit clock signal output to the CXD8517Q (IC751)

50

WST

O

L/R sampling clock signal output to the CXD8517Q (IC751)

51

SCKR

I

Bit clock signal input from the CXD2537R (IC601)

52

GNDQ

—

Ground terminal (for internal logic)

53

VCCQ

—

Power supply terminal (+5V) (for internal logic)

54

GNDS

—

Ground terminal (for SAI, SHI and ONCE output buffer)

55

WSR

I

L/R sampling clock signal input from the CXD2537R (IC601)

56

SDI1

I

Serial data input from the system controller (IC101)

– 87 –

Pin No.

Pin Name

I/O

Function

57

SDI0

I

Playback serial data input from the CXD2537R (IC601)

58

DSO

O

Debug serial data output terminal    Not used (pull up)

59

DSI/OS0

I

Debug serial data input terminal    Not used (fixed at “L”)

60

DSCK/OS1

I/O

Debug serial clock signal in/out terminal    Not used (fixed at “L”)

61

DR

I

Debug request signal input terminal    Not used (fixed at “H”)

62 to 65

MD7 to MD4

I/O

Two-way data bus with the external memory    Not used (open)

66

GNDD

—

Ground terminal (for EMI data bus and GPIO output buffer)

67 to 69

MD3 to MD1

I/O

Two-way data bus with the D-RAM (IC702)

70

VCCD

—

Power supply terminal (+5V) (for EMI data bus and GPIO output buffer)

71

MD0

I/O

Two-way data bus with the D-RAM (IC702)

72

GNDD

—

Ground terminal (for EMI data bus and GPIO output buffer)

73

GPIO3

I

ATRAC block 11.6 msec timing signal input from the CXD2537R (IC601)

74

GPIO2

O

Latch control signal output of the BCK and LRCK signals

75

GPIO1

I

ATRAC interface data EXE signal input from the CXD2537R (IC601)

76

GPIO0

I

Playback direction control signal input from the system controller (IC101)
“L”: RVS, “H”: FWD

77

MRD

O

Data read strobe signal output of the external memory    “L” active    Not used (open)

78

MWR

O

Data write strobe signal output to the D-RAM (IC702)    “L” active

79

MRAS

O

Row address strobe signal output to the D-RAM (IC702)    “L” active

80

MCAS

O

Column address strobe signal output to the D-RAM (IC702)    “L” active