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– 76 –

INDICATION

CODE

RESISTOR

(8BIT x 16)

DECODER

(35BIT x 16)

DECODER

(35BIT x 16)

CODE/COMMAND

CONTROL

CIRCUIT

INDICATION

CONTROL

RESISTOR

INDICATION

CONTROLLER

DIGITAL
OUTPUT
CIRCUIT

CODE

WRITE

SERIAL

RECEIVE

CIRCUIT

OUTPUT

PORT

(2BIT)

CLOCK

GENERATOR

CIRCUIT

RAM WRITE

CODE SELECT

DIG12

|

DIG15

V

CC

2

SEG0

|

SEG26

V

SS

XIN

XOUT

V

CC

1

RES

DIG11

|

DIG0

CS

CLK

DATA

SEG35

|

SEG27

P1

P0

14

15

16

17

18

19

20

21

22

23

|

31

13

1

|

12

SEGMENT OUTPUT CIRCUIT

59

|

33

60

32

VP

64

|

61

1

MODE1(5V)

2

MODE2(7V)

3

C

4

RRC

5

RESET

6

5V

7

VCC

8

NC

9

NC

10

7V

11

PRE GND

12

GND

REF. V

OVER

CURRENT

PROTECT

–

+

OVER

CURRENT

PROTECT

–

+

1

2

3

4

5

VCC

Cd

RESET

INT

GND

+

–

+

–

RESET

SIGNAL

GENERATOR

INTERRUPT

SIGNAL

GENERATOR

2

5

5k

+

–

27k

OVERCURRENT

LIMITTER

OVERHEAT

PROTECTION

REFERENCE

VOLTAGE

GND

ON/OFF

IN

REFERENCE
VOLTAGE

OUT

3

4

1

– 77 –

•

Pin No.

Pin Name

I/O

Function

1

VC

O

Middle point voltage (+2.5V) generation output terminal

2 to 7

A to F

I

Signal input from the optical pick-up detector

8

FI

I

Operational input for the F signal

9

FO

O

Operational output for the F signal

10

PD

I

Light amount monitor input from the optical pick-up block laser diode

11

APCREF

I

Reference voltage input terminal for setting laser power

12

TEMPI

I

Connected to the temperature sensor

13

GND

—

Ground terminal

14

AAPC

O

Laser amplifier output terminal to the automatic power control circuit

15

DAPC

O

Not used (open)

16

TEMPR

O

Output terminal for a temperature sensor reference voltage

17

XRST

I

Reset signal input from the system controller (IC101)    “L”: reset

18

SWDT

I

Writing serial data input from the system controller (IC101)

19

SCLK

I

Serial data transfer clock signal input from the system controller (IC101)

20

XLAT

I

Serial data latch pulse signal input from the system controller (IC101)

21

VREF

O

Reference voltage output terminal    Not used (open)

22

TENV

O

Not used (open)

23

THLD

I

Connected to the external capacitor for set the internal circuit

24

VCC

—

Power supply terminal (+5V)

25

TFIL

I

Connected to the external capacitor for set the internal circuit

26

TE

O

Tracking error signal output to the CXD2535CR (IC121)

27

TLB

I

Adder signal input of the tracking error

28

CSLED

I

Connected to the external capacitor for low-pass filter of the sled error signal

29

SE

O

Sled error signal output to the CXD2535CR (IC121)

30

ADFM

O

FM signal output of the ADIP

31

ADIN

I

Receives a ADIP FM signal in AC coupling

32

ADAGC

I

Connected to the external capacitor for ADIP AGC

33

ADFG

O

ADIP duplex signal (22.05 kHz 

±

 1 kHz) output to the CXD2535CR (IC121)

34

AUX

O

Auxiliary signal (I

3

 signal/temperature signal) output to the CXD2535CR (IC121)

35

FE

O

Focus error signal output to the CXD2535CR (IC121)

36

FLB

I

Adder signal input of the focus error    Not used (open)

37

ABCD

O

Light amount signal (ABCD) output to the CXD2535CR (IC121)

38

BOTM

O

Light amount signal (RF/ABCD) bottom hold output to the CXD2535CR (IC121)

39

PEAK

O

Light amount signal (RF/ABCD) peak hold output to the CXD2535CR (IC121)

40

RFAGC

I

Connected to the external capacitor for RF auto gain control circuit

41

RF

O

Playback EFM RF signal output to the CXD2535CR (IC121)

42

ISET

I

Connected to the external capacitor for set the internal circuit    22 kHz, BPF center frequency

43

AGCI

I

Receives a RF signal in AC coupling

44

RFO

O

RF signal output terminal

45

MORFI

I

Receives a MO RF signal in AC coupling

46

MORFO

O

MO RF signal output terminal

47

I

I

I-V converted RF signal I input from the optical pick-up block detector

48

J

I

I-V converted RF signal J input from the optical pick-up block detector

– 78 –

•

Pin No.

Pin Name

I/O

Function

1

FS256

O

Clock signal (11.2896 MHz) output terminal (MCLK system)    Not used (open)

2

FOK

O

Focus OK signal output to the system controller (IC101)
“H” is output when focus is on (“L”: NG)

3

DFCT

O

Defect on/off selection signal output terminal    Not used

4

SHCK

O

Track jump detection signal output to the system controller (IC101)

5

SHCKEN

I

Track jump detect enable input terminal    Fixed at “H” in this set

6

WRPWR

I

Laser power selection signal input from the system controller (IC101)
“L”: playback mode, “H”: recording mode

7

DIRC

I

Not used (fixed at “H”)

8

SWDT

I

Writing serial data input from the system controller (IC101)

9

SCLK

I

Serial data transfer clock signal input from the system controller (IC101)

10

XLAT

I

Serial data latch pulse signal input from the system controller (IC101)

11

SRDT

O

Reading serial data output to the system controller (IC101)

12

SENS

O (3)

Internal status (SENSE) output to the system controller (IC101)

13

ADSY

O

ADIP sync signal output terminal    Not used (open)

14

SQSY

O

Subcode Q sync (SCOR) output to the system controller (IC101)
“L” is output every 13.3 msec     Almost all, “H” is output

15

DQSY

O

Digital In U-bit CD format subcode Q sync (SCOR) output terminal
“L” is output every 13.3 msec     Almost all, “H” is output    Not used (open)

16

XRST

I

Reset signal input from the system controller (IC101)    “L”: reset

17

TEST4

I

Input terminal for the test (fixed at “L”)

18

CLVSCK

O

System clock signal output of the CLV    Not used (open)

19

TEST5

I

Input terminal for the test (fixed at “L”)

20

DOUT

O

Digital audio signal output terminal when playback mode (for digital optical out/digital coaxial
out)    Not used

21

DIN

I

Digital audio signal input terminal when recording mode (for digital optical in/digital coaxial in)
Not used (fixed at “L”)

22

FMCK

O

FM demodulation clock signal output of the ADIP    Not used (open)

23

ATER

O

ADIP CRC flag output terminal    Error present when “H” output    Not used (open)

24

REC

I

Recording/playback selection signal input from the system controller (IC101)
“L”: playback mode, “H”: recording mode

25

DVSS

—

Ground terminal (digital system)

26

DOVF

I

Validity flag input for the digital audio output    Fixed at “L” in this set

27

DODT

I

Serial data input from the ATRAC encoder (IC501)

28

DIDT

O

Serial data output terminal    Not used

29

DTI

I

Recording audio data input from the ATRAC encoder (IC501)

30

DTO

O (3)

Playback audio data output to the ATRAC decoder (IC601)

31

C2PO

O

C2PO signal (indicate output of the data error status) output to the ATRAC encoder (IC501) and
ATRAC decoder (IC601)
Playback mode: C2PO (“H”), Digital recording mode: digital in validity flag, Analog recording
mode: “L”

32

BCK

O

Serial in/out data bit clock signal (2.8224 MHz) output to the ATRAC encoder (IC501) and
ATRAC decoder (IC601) (MCLK system)

33

LRCK

O

L/R sampling clock signal (44.1 kHz) output to the ATRAC encoder (IC501) and ATRAC
decoder (IC601) (MCLK system)

34

XTAO

O

System clock signal (512Fs=22.5792 MHz) output terminal    Not used (open)

35

XTAI

I

System clock signal (512Fs=22.5792 MHz) input from the ATRAC encoder (IC501)

* I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O.

– 79 –

Pin No.

Pin Name

I/O

Function

36

MCLK

O

MCLK clock signal (22.5792 MHz) output terminal    Not used (open)

37

XBCK

O

Invert output of the BCK (pin #™)    Not used (open)

38

DVDD0

—

Power supply terminal (+5V) (digital system)

39

WDCK

O

Word clock signal (88.2 kHz) output terminal (MCLK system)    Not used (open)

40

RFCK

O

Read frame clock signal (7.35 kHz) output terminal (MCLK system)    Not used (open)

41

WFCK

O

Write frame clock signal (7.35 kHz) output terminal (EFM decoder PLL system when playback
mode, EFM encoder PLL system when recording mode)    Not used (open)

42

GTOP

O

GTOP signal output terminal
Open the playback EFM sync protection window when “H” output    Not used (open)

43

GFS

O

Guard frame sync signal output terminal    The GFS signal becomes “H” when the playback EFM
frame sync and interpolation protection timing match    “L”: NG, “H”: OK
Not used (open)

44

XPLCK

O

EFM decoder PLL clock signal (98Fs=4.3218 MHz) output terminal
PLL is made for XPLCK so that changes in the reversion and falling edge of the EFM PLL clock
and the EFM signal match    Not used (open)

45

EFMO

O

EFM signal output terminal when recording mode

46

RAOF

O

Internal RAM overflow detect signal output terminal (monitor output of decoder)
RAOF is a signal generated when the RAM exceeds the 

±

4 jitter margin    Not used (open)

47

MVCI

I

Oscillation input of the digital in PLL    Not used (fixed at “L”)

48

TEST2

I

Input terminal for the test (fixed at “L”)

49

DIPD

O (3)

Phase comparison output of the digital in PLL
Internal VCO (frequency: low 

→

 “H”), External VCO (frequency low 

→

 “L”)

50

DVSS1

—

Ground terminal (digital system)

51

DICV

I (A)

Internal VCO control voltage input of the digital in PLL

52

DIFI

I (A)

Internal VCO filter input of the digital in PLL

53

DIFO

O (A)

Internal VCO filter output of the digital in PLL

54

AVDD1

—

Power supply terminal (+5V) (analog system)

55

ASYO

O

Playback EFM full-swing output terminal (“L”=VSS, “H”=VDD)

56

ASYI

I (A)

Playback EFM asymmetry comparator voltage input terminal

57

BIAS

I (A)

Playback EFM asymmetry circuit constant current input terminal

58

RFI

I (A)

Playback EFM RF signal input from the CXA1981AR (IC101)

59

AVSS1

—

Ground terminal (analog system)

60

CLTV

I (A)

Internal VCO control voltage input for master clock of the decoder PLL

61

PCO

O (3)

Phase comparison output for master clock of the decoder PLL

62

FILI

I (A)

Filter input for master clock of the decoder PLL

63

FILO

O (3)

Filter output for master clock of the decoder PLL

64

PEAK

I (A)

Light amount signal (RF/ABCD) peak hold input from the CXA1981AR (IC101)

65

BOTM

I (A)

Light amount signal (RF/ABCD) bottom hold input from the CXA1981AR (IC101)

66

ABCD

I (A)

Light amount signal (ABCD) input from the CXA1981AR (IC101)

67

FE

I (A)

Focus error signal input from the CXA1981AR (IC101)

68

AUX1

I (A)

Auxiliary signal (I

3

 signal/temperature signal) input from the CXA1981AR (IC101)

69

VC

I (A)

Middle point voltage (+2.5V) input from the CXA1981AR (IC101)

70

ADIO

O (A)

Monitor output of the A/D converter input signal    Not used (open)

71

TEST3

I (A)

Input terminal for the test (fixed at “L”)

72

AVDD2

—

Power supply terminal (+5V) (analog system)

73

ADRT

I (A)

A/D converter operational range upper limit voltage input terminal (fixed at “H” in this set)

74

ADRB

I (A)

A/D converter operational range lower limit voltage input terminal (fixed at “L” in this set)

75

AVSS2

—

Ground terminal (analog system)

76

SE

I (A)

Sled error signal input from the CXA1981AR (IC101)

* I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O.