Sony MDS-B6P Service Manual ▷ View online
— 79 —
Pin No.
Pin Name
I/O
Function
Middle point voltage (2.5V) generation output
Input of signal from optical block detector
F operation amplifier input
F operation amplifier output
Front monitor. Connected to photo diode
Input pin for setting laser power
Temperature sensor connection input
Ground
APC LD amplifier output
Not used
Temperature sensor reference voltage output
Input of reset signal from Q403
Reset: “L”
Input of write data signal from system controller (IC301)
Input of clock signal from system controller (IC301)
Input of latch signal from system controller (IC301)
Reference voltage output (Not used)
Not used
Not used (Connected to VC)
Power supply (+5V)
Not used
Output of tracking error signal to CXD2535CR (IC121)
Input of add signal to tracking error
Sled error LPF input
Output of sled error signal to CXD2535CR (IC121)
ADIP FM signal output
Inputs ADIP FM signal by AC coupling
Connection of external capacitor for ADIP AGC
Output of ADIP dual FM signal to CXD2535CR (IC121) (22.05 kHz±1 kHz)
Output of auxiliary signal to CXD2535CR (IC121)
Output of focus error signal to CXD2535CR (IC121)
Not used
Output of light amount signal to CXD2535CR (IC121)
Output of bottom hold signal of light amount signal to CXD2535CR (IC121)
Output of peak hold signal of light amount signal to CXD2535CR (IC121)
Connection of RF AGC circuit external capacitor
Output of playback EFM RF signal to CXD2535CR (IC121)
Internal circuit constant setting input
22 kHz BPF center frequency
Inputs RF signal by AC coupling
Output of RF signal
Inputs MO RF signal by AC coupling
Output of MO RF signal
Input of signal from optical block detector
O
I
I
O
I
I
I
–
O
O
O
I
I
I
I
O
O
I
–
I
O
I
I
O
O
I
I
O
O
O
I
O
O
O
I
O
I
I
O
I
O
I
VC
A to F
FI
FO
PD
APCREF
TEMPI
GND
AAPC
DAPC
TEMPR
XRST
SWDT
SCLK
XLAT
VREF
TENV
THLD
VCC
TFIL
TE
TLB
CSLED
SE
ADFM
ADIN
ADAGC
ADFG
AUX
FE
FLB
ABCD
BOTM
PEAK
RFAGC
RF
ISET
AGCT
RFO
MORFI
MORFO
I, J
1
2 to 7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47, 48
• IC101 RF Amplifier (CXA1981AR)
5-13. IC PIN FUNCTIONS
— 80 —
• IC121 Digital signal procesor, digital servo processor, EFM/ACIRC encoder/decoder (CXD2535CR)
FS256
FOK
DFCT
SHCK
SHCKEN
WRPWR
DIRC
SWDT
SCLK
XLAT
SRDT
SENS
ADSY
SQSY
DQSY
XRST
TEST4
CLVSCK
TEST5
DOUT
DIN
FMCK
ADER
REC
DVSS
DOVF
DODT
DIDT
DTI
DTO
C2PO
BCK
LRCK
XTAO
XTAI
MCLK
XBCK
DVDD
WDCK
RFCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
O
O
O
O
I
I
I
I
I
I
O
O(3)
O
O
O
I
I
O
I
O
I
O
O
I
–
I
I
O
I
O(3)
O
O
O
O
I
O
O
–
O
O
Function
Pin No.
Pin Name
I/O
11.2896 MHz clock output (MCLK) (Not used)
Output of FOK signal to system controller (IC301)
Outputs “H” when focus is set
Outputs defect ON/OFF switching signal (Not used)
Outputs track jump detection signal to system controller (IC301)
Track jump detection enable input (Fixed at “H”)
Inputs laser power switching signal from system controller (IC301)
Not used (Fixed at “H”)
Inputs write data signal from system controller (IC301)
Inputs serial clock signal from system controller (IC301)
Inputs serial latch signal from system controller (IC301)
Outputs write data signal to system controller (IC301)
Outputs internal status (SENSE) to system controller (IC301)
ADIP sync signal output (Not used)
Output subcode Q sync (SCOR) to system controller (IC301)
Outputs “L” every 13.3 msec
Outputs “H” at all most mostly
Outputs digital-in U-bit CD format subcode Q sync (SCOR) to system controller (IC301)
Outputs “L” every 13.3 msec Outputs “H” at all most mostly
Inputs reset signal from Q403
Reset: “L”
Test input (Fixed at “L”)
Not used
Test input (Fixed at “L”)
Digital audio signal output
Digital audio signal input (Not used)
ADIP FM demodulation clock signal output
ADIP CRC flag output
“H”:Error
Input of recording/playback switching signal from system controller (IC301)
Recording: “H”
Playback: “L”
Ground (Digital)
Digital audio output validity flag input (Fixed at “L”)
Input of data for digital audio output from CXD8633Q (IC901)
Output of data for digital audio input
Input of recording audio data signal from CXD2536CR (IC401)
Output of playback audio data signal to CXD2536CR (IC401)
Outputs C2PO signal to CXD2536CR (IC401) (Output indicating data error status)
Playback: C2PO (“H”)
Digital recording: D.In-Vflag
Analog recording: “L”
Outputs bit clock signal (2.8224 MHz) to CXD2536CR (IC401) (MCLK)
Outputs L/R clock signal (44.1 kHz) to CXD2536CR (IC401) (MCLK)
For crystal
Input of system clock (512fs) for crystal
MCLK clock (22.5792 MHz) signal output (Not used)
Pin 32 (BCK) inversion output (Not used)
Power supply (+5V) (Digital)
WDCK clock (88.2 kHz) signal output (MCL) (Not used)
RFCK clock (7.35 kHz) signal output (MCLK) (Not used)
— 81 —
WFCK
GTOP
GFS
XPLCK
EFMO
RAOF
MVCI
TEST2
DIPD
DVSS
DICV
DIFI
DIFO
AVDD
ASYO
ASYI
BIAS
RFI
AVSS
CLTV
PCO
FILI
FILO
PEAK
BOTM
ABCD
FE
AUX1
VC
ADIO
TEST3
AVDD
ADRT
ADRB
AVSS
SE
TE
AUX2
DCHG
APC
O
O
O
O
O
O
I
I
O(3)
–
I(A)
I(A)
O(A)
–
O
I(A)
I(A)
I(A)
–
I(A)
O(3)
I(A)
O(3)
I(A)
I(A)
I(A)
I(A)
I(A)
I(A)
O(A)
I(A)
–
I(A)
I(A)
–
I(A)
I(A)
I(A)
I(A)
I(A)
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
WFCK clock (7.35 kHz) signal output
(Playback: EFM decoder PLL
Recording: EFM encoder PLL) (Not used)
“H”: Opens playback EFM frame sync protection window (Not used)
“H”: Playback EFM sync and interpolation protection timing match (Not used)
EFM decoder PLL clock output (98 fs=4.3218 MHz)
Falling edge and EFM signal edge match (Not used)
EFM signal output (Recording) (Not used)
Internal RAM overflow detection signal output (decoder monitor output)
Outputs “H” when the disc rotation exceeds ±4F jitter margin during playback (Not used)
Digital-in PLL oscillation input (Fixed at “L”)
Test pin (Fixed at “L”)
Digital-in PLL phase comparison output
Internal VCO: (Frequency: Lown“H”)
External VCO: (Frequency: Lown“L”) (Not used)
Ground (Digital)
Digital-in PLL internal VCO control voltage input
Filter input when digital-in PLL internal VCO is used
Filter output when digital-in PLL internal VCO is used (Not used)
Power supply (+5V) (Analog)
Playback EFM full-swing output (L=VSS, H=VDD)
Playback EFM asymmetry comparate voltage input
Playback EFM asymmetry circuit constant current input
Inputs playback EFM RF signal from CXA1981AR (IC101)
Ground (Analog)
Decoder PLL master clock PLL VCO control voltage input
Decoder PLL master clock PLL phase comparison output
Decoder PLL master clock PLL filter input
Decoder PLL master clock PLL filter output
Inputs peak hold signal for light amount signal from CXA1981AR (IC101)
Inputs bottom hold signal for light amount signal from CXA1981AR (IC101)
Light amount signal from CXA1981AR (IC101)
Input of focus error signal from CXA1981AR (IC101)
Input of auxiliary signal from CXA1981AR (IC101)
Input of middle point voltage (+2.5V) from CXA1981AR (IC101)
A/D converter input signal monitor output (Not used)
Test input (Fixed at “L”)
Power supply (+5V) (Analog)
A/D converter operation range upper limit voltage input (Fixed at “H”)
A/D converter operation range lower limit voltage input (Fixed at “L”)
Ground (Analog)
Input of sled error signal from CXA1981AR (IC101)
Input of tracking error signal from CXD1981AR (IC101)
Auxiliary input 2 (Fixed at “L”)
Connected to ground
Laser APC input (Fixed at “L”)
Pin No.
Pin Name
I/O
Function
— 82 —
Test pin (Fixed at “L”)
Input of ADIP dual FM signal from CXA1981AR (IC101) (22.05 kHz ±1 kHz)
(TTL Schmidt input)
Test pin (Fixed at “L”)
Laser APC signal output
Tracking servo drive signal output (–)
Tracking servo drive signal output (+)
Focus servo drive signal output (+)
Power supply (+5V) (Digital)
Focus servo drive signal output (–)
176.4 kHz clock signal output (MCLK)
Sled servo drive signal output (–)
Sled servo drive signal output (+)
Spindle servo drive signal output (–)
Spindle servo drive signal output (+)
Not used
Not used (Fixed at “H”)
Not used
Off track signal output (Not used)
Traverse count signal output (Not used)
Ground (Digital)
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
TEST1
ADFG
TS25
LDDR
TRDR
TFDR
FFDR
DVDD
FRDR
FS4
SRDR
SFDR
SPRD
SPFD
DCLO
DCLI
XDCL
OFTRK
COUT
DVSS
I
I
I
O
O
O
O
–
O
O
O
O
O
O
O
I
O
O
O
–
Function
Pin No.
Pin Name
I/O
* (3) of I/O is 3-state output, (A) is analog output.
Click on the first or last page to see other MDS-B6P service manuals if exist.