Sony MDS-B5 Service Manual ▷ View online
— 96 —
48, 49
50
51
52 to 55
56 to 60
61
62
63
64
65
66
67
68, 69
70, 71
72 to 74
75
76
77
78
79
80
81
82
82
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
A11, A10
VSS
VDD
A03 to A00
A04 to A08
XOE
XCAS
VSS
XCS
A09
XRAS
XWE
D1, D0
D2, D3
D4 to D6
VSS
D7
ERR
EXTC2R
BUSY
EMP
FUL
EQL
MDLK
CPSY
CTMD0
CTMD1
SPO
VSS
MDSY
LRCK
BCK
C2PO
DATA
DIDT
DODT
DIRCPB
MIN
SPOSL
MCK
VSS
O
—
—
O
O
O
O
—
O
O
O
O
I/O
I/O
I/O
—
I/O
I/O
I
O
O
O
O
O
O
O
O
O
—
O
I
I
I
I/O
I
O
O
I
I
O
—
Output of address signal to RAM (IC402)
Ground
Power supply (+5V)
Output of address signal to RAM (IC402)
Output of address signal to RAM (IC402)
Output of output enable control signal to RAM (IC402)
Output of column address strobe signal to RAM (IC402)
Ground
Output of chip select signal to RAM (IC402) (Not used)
Output of address signal to RAM (IC402)
Output of row address strobe signal to RAM (IC402)
Output of read/write control signal to RAM (IC402)
Input/output of data signal to/from RAM (IC402)
Data signal input/output (Not used)
Ground
Data signal input/output (Not used)
Input/output of error (C2PO) data to external RAM (Not used)
External RAM selection input for error data writing (“H”: External RAM) (Fixed at “L”)
RAM access BUSY signal output (Not used)
EMPTY or immediately before FULL of ATRAC data (When DSC=ASC+1: “H”)
(Not used)
FULL or immediately before EMPTY of ATRAC data (When ASC=DSC+1: “H”)
(Not used)
ATRAC data EMPTY (When DSC=ASC: “H”) (Not used)
Indicates recording/playback data main/sub (“H”: Sub, Linking: “L”: Main) (Not used)
Interpolation sync signal output (Not used)
DSC counter mode output (Not used)
System clock 512fs signal output
Ground
Main data sync detection signal output (Not used)
Input of L/R clock signal from CXD2535CR (IC121) (44.1 kHz)
Input of bit clock signal from CXD2535CR (IC121) (2.8224 MHz)
Input of C2PO signal from CXD2535CR (IC121) (Shows data error status)
Playback:C2PO (“H”). Digital recording: D.In-Vflag. Analog recording: “L”
Recording:Output of recording audio data signal to CXD2535CR (IC121)
Playback:Input of playback audio data signal from CXD2535CR (IC121)
Input of digital audio input data from CXD2535CR (IC121)
Output of digital audio output data to CXD2535CR (IC121)
Disc drive and EFM encoder/decoder recording/playback mode output (Not used)
Input of defect ON/OFF switching signal
Pin 87 (SPO) input/output switching input (“L”:IN. “H”:OUT) (Fixed at “H”)
RAM controller internal master clock output (Not used)
Ground
Function
Pin No.
Pin Name
I/O
— 97 —
• IC407 Shock-Proof Memory Controller, ATRAC Encoder/Decoder (CXD2536CR)
Pin No.
Pin Name
I/O
Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18 to 21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45 to 47
VDD
SWDT
SCK
XLAT
SRDT
SENSE
SCMD0
SCMD1
XINT
RCPB
WRMN
TX
VSS
SICK
IDSL
XILT
XRST
TS0 to TS3
EXIR
SASL
SNGLE
VSS
AIRCPB
XRQ
ADTO
ADTI
XALT
ACK
AC2
LCHST
EXE
MUTE
OSCO
OSCI
VSS
ATT
F86
DOUT
ADIN
ABCK
ALRCK
SA2 to SA0
—
I
I
I
O/Z
O/Z
I
I
O
I
I
I
—
I
I
I
I
I
I
I
I
—
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
—
I/O
O
O
I
O
O
O
Power supply (+5V)
Input of write data signal from system controller (IC301)
Input of serial clock signal from system controller (IC301)
Input of serial latch signal from system controller (IC301)
Output of read data signal to system controller (IC301)
Output of internal status (SENSE) to system controller (IC301) (Not used)
Input of serial command control mode (Fixed at “H”)
Output of interrupt status to system controller (IC301)
Recording/playback switching input (Fixed at “L”)
Input of write/monitor mode switching signal (Fixed at “L”)
Input of write data transmission timing from system controller (IC301)
Also used as magnetic field head ON/OFF output
Ground
Chip reservation (Fixed at “L”)
Chip reservation (Fixed at “H”)
Input of reset signal from Q403. Reset: “L”
Test pin (Fixed at “L”)
Chip reservation (Fixed at “L”)
Block selection in single use. “L”: ATRAC. “H”: RAM controller (Fixed at “H”)
Normally fixed at “L. Fixed at “H” when used as ATRAC or RAM controller for single
(Fixed at “H”)
Ground
Output of ATRAC and external audio block recording/playback mode signal
ATRAC I/F XRQ signal input/output
ATRAC decode data signal input/output
ATRAC encode data signal input/output
ATRAC I/F XALT signal input/output
ATRAC I/F ACK signal input/output
ATRAC I/F error data signal input/output (Not used)
ATRAC I/F Lch start data signal input/output (Not used)
ATRAC I/F EXE signal input/output (Not used)
ATRAC I/F MUTE signal input/output (Not used)
Clock output (49.152 MHz) (Not used)
Clock input (49.152 MHz) (Not used)
Ground
ATRAC I/F ATT signal input/output (Not used)
ATRAC block 11.6 msec timing signal output (Not used)
Output of monitor/decode audio data signal (Not used)
Input of recording signal (Not used)
Output of bit clock signal (Not used)
Output of L/R clock to A/D and D/A converters (Not used)
— 98 —
48, 49
50
51
52 to 55
56 to 60
61
62
63
64
65
66
67
68, 69
70, 71
72 to 74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
A11, A10
VSS
VDD
A03 to A00
A04 to A08
XOE
XCAS
VSS
XCS
A09
XRAS
XWE
D1, D0
D2, D3
D4 to D6
VSS
D7
ERR
EXTC2R
BUSY
EMP
FUL
EQL
MDLK
CPSY
CTMD0
CTMD1
SPO
VSS
MDSY
LRCK
BCK
C2PO
DATA
DIDT
DODT
DIRCPB
MIN
SPOSL
MCK
VSS
O
—
—
O
O
O
O
—
O
O
O
O
I/O
I/O
I/O
—
I/O
I/O
I
O
O
O
O
O
O
O
O
I
—
O
I
I
I
I/O
I
O
O
I
I
O
—
Address signal output (Not used)
Ground
Power supply (+5V)
Output of address signal to RAM (IC408)
Output of address signal to RAM (IC408)
Output of output enable control signal to RAM (IC408)
Output of column address strobe signal to RAM (IC408)
Ground
Output of chip select signal to RAM (IC408) (Not used)
Output of address signal to RAM (IC408)
Output of row address strobe signal to RAM (IC408)
Output of read/write control signal to RAM (IC408)
Input/output of data signal to/from RAM (IC408)
Data signal input/output (Not used)
Ground
Data signal input/output (Not used)
Input/output of error (C2PO) data to external RAM (Not used)
External RAM selection input for error data writing (“H”: External RAM) (Fixed at “L”)
RAM access BUSY signal output (Not used)
EMPTY or immediately before FULL of ATRAC data (When DSC=ASC+1: “H”)
(Not used)
FULL or immediately before EMPTY of ATRAC data (When ASC=DSC+1: “H”)
(Not used)
ATRAC data EMPTY (When DSC=ASC: “H”) (Not used)
Indicates recording/playback data main/sub (“H”: Sub, Linking: “L”: Main) (Not used)
Interpolation sync signal output (Not used)
DSC counter mode output (Not used)
Input of system clock (512fs) signal from CXD2536CR (IC401)
Ground
Main data sync detection signal output (Not used)
Input of L/R clock signal from CXD2535CR (IC121) (44.1 kHz)
Input of bit clock signal from CXD2535CR (IC121) (2.8224 MHz)
Input of C2PO signal from CXD2535CR (IC121) (Shows data error status)
Playback:C2PO (“H”). Digital recording: D.In-Vflag. Analog recording: “L”
Recording:Output of recording audio data signal to CXD2535CR (IC121)
Playback:Input of playback audio data signal from CXD2535CR (IC121)
Input of digital audio input data (Not used)
Output of digital audio output data (Not used)
Disc drive and EFM encoder/decoder recording/playback mode output (Not used)
Input of defect ON/OFF switching signal (Fixed at “L”)
Pin 87 (SPO) input/output switching input (“L”:IN. “H”:OUT) (Fixed at “L”)
RAM controller internal master clock output (Not used)
Ground
Function
Pin No.
Pin Name
I/O
— 99 —
• IC409 Sampling Rate Converter (CXD8517Q)
Data input
Input data fs word clock input (Schemidt)
Input data bit clock input
Input data format setting input 0 (Fixed at “L”)
Input data format setting input 1 (Fixed at “L”)
+5V power supply
Input data fs reference clock input (512fs, 384fs, 256fs, 128fs)
Output data format setting input 0 (Fixed at “L”)
Output data format setting input 1 (Fixed at “L”)
Initializing input (Schmidt). “L”: Initializing, “H”: Normal operation
Not used
Ground
Inverter input for oscillating the crystal oscillator (512fo master clock input)
Inverter output for oscillating the crystal oscillator (Not used)
+5V power supply
Oscillation clock division output: 256fs (Not used)
Ground
Input data through output mode setting input. “L”: Normal operation, “H”: Through
(When through: Effective operation output only for deemphasis, attenuation) (Fixed at “L”)
FI128 clock input division ratio setting input (Fixed at “L”)
FI128 clock input division ratio setting input (Fixed at “L”)
Test input 0 (Not used)
Not used
Test input 1 (Fixed at “L”)
Test input 2 (Fixed at “L”)
Test input 3 (Fixed at “L”)
fs conversion ratio measurement condition monitor output (Not used)
+5V power supply
Not used
Data output (fso output)
Output data bit clock input/output
Output data fs word clock input/output
Not used
Data output mute setting input. “L”: Mute, “H”: Normal operation
Synchronized with LRCK (“0" data only for DATAO output) (Fixed at “H”)
Deemphasis setting input. “L”: OFF, “H”: ON (Fixed at “L”)
Deemphasis setting output fso frequency selection input 1 (Fixed at “L”)
Deemphasis setting output fso frequency selection input 2 (Fixed at “L”)
Ground
Attenuation, mode setting data latch pulse input
Attenuation, mode setting clock input
Attenuation, mode setting data input
Sync mode selection. “L”: Slave, “H”: Master (Fixed at “L”)
Not used
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
DATAI
LRCKI
BCKI
MI0
MI1
VDD
FI128
MO0
MO1
INIT
NC
GND
XI
XO
VDD
XO2
GND
PASS
FIS0
FIS1
TEST
NC
NC
TEST1
TEST2
TEST3
STA
VDD
NC
DATAO
BCKO
LRCKO
NC
NC
MUTE
DEMP
FS1
FS2
GND
XLAT
SCK
SWDT
SLAVE
NC
I
I
I
I
I
—
I
I
I
I
—
—
I
O
—
O
—
I
I
I
O
—
—
I
I
I
O
—
—
O
I/O
I/O
—
—
I
I
I
I
—
I
I
I
I
—
Function
I/O
Pin No.
Pin Name
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