Sony ICF-CD555TV Service Manual ▷ View online
49
ICF-CD555TV
Pin No.
Pin Name
I/O
Description
76
RESET
I
System reset signal input from the reset signal generator “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
77
A MUTE
O
Audio muting on/off control signal output terminal “L”: muting on
78
RADIO ON
O
Power on/off control signal output for the radio section “L”: power on
79
CD ON
O
Power on/off control signal output for the CD section “L”: power on
80
TIMER LED
O
LED drive signal output of the TIMER “L”: LED on
50
ICF-CD555TV
TV BOARD IC1401
µ
PD789477GC-A45-8BT (TV SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1 to 25
NC
—
Not used
26
TFT TEST MODE
I
Monitor test mode setting terminal “H”: test mode on
27 to 29
NC
—
Not used
30
T-AGC
O
TV AGC on/off control signal output to the TV tuner unit
31
T-MUTE
O
TV muting on/off control signal output to the TV tuner unit “H”: muting on
32
T-SDATA
O
Serial data output to the TV tuner unit
33
T-SCL
O
Serial data transfer clock signal output to the TV tuner unit
34
T-A MUTE
O
TV audio muting on/off control signal output terminal “H”: muting on
35, 36
NC
—
Not used
37
TFT OPEN
I
Monitor open/close detection signal input terminal “L”: open, “H”: close
38
AVDD
—
Power supply terminal (+3.3V) (for A/D converter)
39 to 45
NC
—
Not used
46
T-AFT
I
TV AFT detection signal input from the TV tuner unit (A/D input)
47
AVSS
—
Ground terminal (for A/D converter)
48
NC
—
Not used
49
EEPROM-SDA
I/O
Two-way data bus with the EEPROM
50
EEPROM-SCL
O
Serial data transfer clock signal output to the EEPROM
51
NC
—
Not used
52
VSYNC
I
Vertical sync signal input from the RGB decoder
53
OSD-CS
O
Chip select signal output to the OSD driver
54
OSD-DATA
O
Serial data output to the OSD driver
55
OSD-CLK
O
Serial data transfer clock signal output to the OSD driver
56
TV DATA-SI
I
Serial data input from the system controller
57
TV DATA-SO
O
Serial data output to the system controller
58
TV DATA-CLK
I
Serial data transfer clock signal input from the system controller
59
NC
—
Not used
60
TFT-ON
O
Power on/off control signal output for back light unit “H”: power on
61
ZOOM
O
Screen size selection signal output to the LCD controller “H”: zoom screen
62
JUST
O
Screen size selection signal output to the LCD controller “H”: wide screen
63, 64
SIDE1, SIDE2
O
Screen size selection signal output to the LCD controller
65
HSYNCLOCK
I
Horizontal sync detection signal input from the RGB decoder
66
SDA
O
Serial data output to the RGB decoder
67
SCK
O
Serial data transfer clock signal output to the RGB decoder
68
NC
—
Not used
69
VPP/VSS
I
Connected to the ground
70
XT1
I
System clock input terminal Not used
71
XT2
O
System clock output terminal Not used
72
VDD
—
Power supply terminal (+3.3V)
73
VSS
—
Ground terminal
74
X1
I
System clock input terminal (4.19 MHz)
75
X2
O
System clock output terminal (4.19 MHz)
76
RESET
I
System reset signal input from the system controller “L”: reset
77
TV/VIDEO
O
TV/video selection signal output terminal “L”: TV, “H”: video
78
T-MODE
O
Audio mode selection signal output to the TV tuner unit
79
T-FMONO
O
Audio mode selection signal output to the TV tuner unit
80
MONITOR ON
O
Power on/off control signal output for LCD module “H”: power on
51
ICF-CD555TV
TV BOARD IC1551
µ
PD6467GR-546-E1 (OSD DRIVER)
Pin No.
Pin Name
I/O
Description
1
SCLK
I
Serial data transfer clock signal input from the TV system controller
2
CSN
I
Chip select signal input from the TV system controller
3
DATA
I
Serial data input from the TV system controller
4
PCL
I
Clear signal input after the power supply rises
5
VDD
—
Power supply terminal (+3.3V)
6
CMDCT
I
Command LSB/MSB first input selection signal input terminal
“L”: LSB first, “H”: MSB first Fixed at “H” in this set
“L”: LSB first, “H”: MSB first Fixed at “H” in this set
7
OSC OUT
O
Output terminal from the clock generator circuit
8
OSC IN
I
Input terminal from the clock generator circuit
9
TEST
I
Test mode setting terminal “H”: test mode, normally fixed at “L”
10
GND
—
Ground terminal
11
BLK1
O
Blanking signal output terminal Not used
12
VC1
O
Character signal output terminal Not used
13
BLK2
O
Blanking signal output terminal Not used
14
VC2
O
Character signal output terminal Not used
15
BLK
O
Blanking signal output to the RGB decoder
16 to 18
VR, VG, VB
O
Character signal output to the RGB decoder
19
VSYNCN
I
Vertical sync signal input from the RGB decoder
20
HSYNCN
I
Horizontal sync signal input from the RGB decoder
52
ICF-CD555TV
TV BOARD IC1601 MN5814 (LCD CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
SYNCIN
I
Composite sync signal input terminal Not used
2
HSYNCIN
I
Horizontal sync signal input from the RGB decoder
3, 4
SIDE2, SIDE1
I
Screen size selection signal input from the TV system controller
5
VDBIN
I
Vertical sync signal input from the RGB decoder
6
HOUT
O
Horizontal sync signal output terminal Not used
7
VOUT
O
Vertical sync signal output terminal Not used
8
BLACK
O
Black signal output to the RGB decoder
9 to 11
VPOS3 to VPOS1
I
Vertical display position selection signal input terminal
12
ZOOM
I
Screen size selection signal input from the TV system controller “H”: zoom screen
13
UD
I
Above and below scan direction selection signal input terminal Not used
14
POL
O
Polarity inversion signal of reflection and opposite output to the RGB decoder
15
INTEXT
I
Composite/separate sync selection signal input terminal
16
CPV
O
Gate driver clock signal output to the liquid crystal display module
17 to 19
OEV3 to OEV1
O
Gate driver output enable pulse signal output to the liquid crystal display module
20
STV1
O
Gate driver start pulse signal output to the liquid crystal display module
21
OEH
O
Source driver output enable pulse signal output to the liquid crystal display module
22
ZOOMC
O
Screen size selection signal output terminal Not used
23, 24
STH1, STH2
O
Source driver start pulse signal output to the liquid crystal display module
25
CPH3
O
Source driver clock signal output to the liquid crystal display module
26
STV2
O
Gate driver start pulse signal output to the liquid crystal display module
27
CPH2
O
Source driver clock signal output to the liquid crystal display module
28
R/L
I
Left and right scan direction selection signal input terminal Not used
29
CPH1
O
Source driver clock signal output to the liquid crystal display module
30
HDOT2
I
Mode selection signal input for number of display pixel
31
JUST
I
Screen size selection signal input from the TV system controller “H”: wide screen
32
POSSET
I
Horizontal display position and vertical display position offset selection signal input terminal
33
PD
O
Phase comparation output terminal
34
QVDZMSEL
I
Screen size selection signal input terminal
35
VDD (A)
—
Power supply terminal (+3.3V)
36
VCO1
I
VCO signal and system clock signal input terminal
37
VCO0
O
System clock signal output terminal
38
VSS (A)
—
Ground terminal
39
RESET
I
System reset signal input terminal
40
HDOT1
I
Mode selection signal input for number of display pixel
41
UONS
I
Screen size selection signal input terminal
42 to 45 HPOS4 to HPOS1
I
Horizontal display position selection signal input terminal
46
N/P
I
NTSC/PAL selection signal input terminal “L”: NTSC, “H”: PAL Fixed at “L” in this set
47
VDD (D)
—
Power supply terminal (+3.3V)
48
VSS (D)
—
Ground terminal
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