Sony HTP-78SS / HT-SF1100 / HT-SS1100 / STR-KS1100 Service Manual ▷ View online
45
STR-KS1100
Pin No.
Pin Name
I/O
Description
49
MD0
I
CPU operation mode setting signal input terminal
50
MD1
I
Setting terminal for the CPU operation mode Fixed at "H" in this set
51
MD2
I
CPU operation mode setting signal input terminal
52
RDS CLK
I
RDS serial data transfer clock signal input from the tuner (FM/AM)
53
RDS DATA
I
RDS serial data input from the tuner (FM/AM)
54
SIRCS
I
SIRCS signal input from the remote control receiver
55
ADCC_INT
I
Auto digital cinema calibration interrupt signal input terminal
56
POWER KEY
I
Power key input terminal
57
NO USE
-
Not used
58
LAT2
O
Latch control signal output to the stream processor
59
TV LED
O
LED rive signal output of the TV indicator "H": LED on
60
SA-CD LED
O
LED rive signal output of the SA-CD/CD indicator "H": LED on
61
SHIFT
O
Shift clock signal output to the stream processor
62
SCDT
O
Serial data output to the stream processor
63
SOFT_MUTE
O
Soft muting on/off control signal output to the stream processor "L": muting on
64
INT
O
Reset signal output to the stream processor "L": reset
65
LAT1
O
Latch control signal output to the stream processor
66
NO USE
-
Not used
67
TUNER LED
O
LED drive signal output of the TUNER indicator "H": LED on
68
OVF
I
Over flow detection signal input from the stream processor "L": over flow
69
LAT3
O
Latch control signal output to the stream processor
70
VOLB
I
Jog dial pulse input from the rotary encoder (for MASTER VOLUME) (A phase input)
71
VOLA
I
Jog dial pulse input from the rotary encoder (for MASTER VOLUME) (B phase input)
72
FL_DIN
O
Serial data output to the fluorescent indicator tube
73
FL_CLK
O
Serial data transfer clock signal output to the fluorescent indicator tube
74
FL_STB
O
Strobe signal output to the fluorescent indicator tube
75
NO USE
-
Not used
76
DC_SD
I
DC shut down signal input terminal "L": shut down
77
RSTX
I
System reset signal input from the reset signal generator "L": reset
For several hundreds msec. after the power supply rises, "L" is input, then it change to "H"
For several hundreds msec. after the power supply rises, "L" is input, then it change to "H"
78
OVFW
I
Over flow detection signal input from the stream processor "L": over flow
79
X1A
I
Sub system clock input terminal Not used
80
X0A
O
Sub system clock output terminal Not used
81
VSS
-
Ground terminal
82
X0
I
Main system clock input terminal (24 MHz)
83
X1
O
Main system clock output terminal (24 MHz)
84
VCC3
-
Power supply terminal (+3.3V)
85
T.CLK
O
PLL serial data transfer clock signal output to the tuner (FM/AM)
86
T.DATA
O
PLL serial data output to the tuner (FM/AM)
87
SLATCH
O
Latch control signal output to the tuner (FM/AM)
88
T_DO
I
PLL serial data input from the tuner (FM/AM)
89
T_MUTE (NC)
O
Tuner muting on/off control signal output terminal Not used
90
ST (NC)
I
FM stereo detection signal input terminal Not used
91
P.CONT3
O
Power on/off control signal output terminal "H": power on
92
LRCK_SW
O
DSP clock selection signal output terminal Not used
93
XMODE
O
System reset signal output to the digital audio interface receiver "L": reset
94
CKSEL1
O
Output clock selection signal output to the digital audio interface receiver
95
CLK
O
Serial data transfer clock signal output to the digital audio interface receiver
46
STR-KS1100
Pin No.
Pin Name
I/O
Description
96
CE
O
Chip enable signal output to the digital audio interface receiver
97
DI
O
Serial data output to the digital audio interface receiver
98
DO
I
Serial data input from the digital audio interface receiver
99
ERROR
I
PLL lock error signal and data error flag input from the digital audio interface receiver
100
XSTATE
I
Source clock selection monitor input from the digital audio interface receiver
47
STR-KS1100
HDMI BOARD IC5001 TMDS341PFCR (HDMI RECEIVER, HDMI TRANSCEIVER)
Pin No.
Pin Name
I/O
Description
1
NC
-
Not used
2
SDA1
I/O
I2C two-way data bus with the HDMI VIDEO 2/BD IN jack
3
SCL1
I
I2C clock signal input from the HDMI VIDEO 2/BD IN jack
4
GND
-
Ground terminal
5
B11
I
TMDS clock signal (negative) input from the HDMI VIDEO 2/BD IN jack
6
A11
I
TMDS clock signal (positive) input from the HDMI VIDEO 2/BD IN jack
7
VCC
-
Power supply terminal (+3.3V)
8
B12
I
TMDS data (negative) input from the HDMI VIDEO 2/BD IN jack
9
A12
I
TMDS data (positive) input from the HDMI VIDEO 2/BD IN jack
10
GND
-
Ground terminal
11
B13
I
TMDS data (negative) input from the HDMI VIDEO 2/BD IN jack
12
A13
I
TMDS data (positive) input from the HDMI VIDEO 2/BD IN jack
13
VCC
-
Power supply terminal (+3.3V)
14
B14
I
TMDS data (negative) input from the HDMI VIDEO 2/BD IN jack
15
A14
I
TMDS data (positive) input from the HDMI VIDEO 2/BD IN jack
16
GND
-
Ground terminal
17
VCC
-
Power supply terminal (+3.3V)
18
VSADJ
I
TMDS compliant voltage swing control signal input terminal Not used
19
PRE
I
Output de-emphasis setting terminal "L": 0 dB, "H": 3 dB Fixed at "L" in this set
20
NC
-
Not used
21
S1
I
Source selection signal input from the system controller
22, 23
S2, S3
I
Source selection signal input terminal Not used
24
GND
-
Ground terminal
25
Y4
O
TMDS data (positive) output to the HDMI OUT jack
26
Z4
O
TMDS data (negative) output to the HDMI OUT jack
27
VCC
-
Power supply terminal (+3.3V)
28
Y3
O
TMDS data (positive) output to the HDMI OUT jack
29
Z3
O
TMDS data (negative) output to the HDMI OUT jack
30
GND
-
Ground terminal
31
Y2
O
TMDS data (positive) output to the HDMI OUT jack
32
Z2
O
TMDS data (negative) output to the HDMI OUT jack
33
VCC
-
Power supply terminal (+3.3V)
34
Y1
O
TMDS data (positive) output to the HDMI OUT jack
35
Z1
O
TMDS data (negative) output to the HDMI OUT jack
36, 37
GND
-
Ground terminal
38
SCL_SINK
O
I2C clock signal output to the HDMI OUT jack
39
SDA_SINK
I/O
I2C two-way data bus with the HDMI OUT jack
40
HPD_SINK
I
Hot plug detection signal input terminal for the HDMI OUT jack
41
NC
-
Not used
42
OEB
I
Chip enable signal input from the system controller
43
VCC
-
Power supply terminal (+3.3V)
44
HPD3
O
Hot plug detection signal output terminal Not used
45
SDA3
I/O
I2C two-way data bus terminal Not used
46
SCL3
I
I2C clock signal input terminal Not used
47
GND
-
Ground terminal
48
B31
I
TMDS clock signal (negative) input terminal Not used
48
STR-KS1100
Pin No.
Pin Name
I/O
Description
49
A31
I
TMDS clock signal (positive) input terminal Not used
50
VCC
-
Power supply terminal (+3.3V)
51
B32
I
TMDS data (negative) input terminal Not used
52
A32
I
TMDS data (positive) input terminal Not used
53
GND
-
Ground terminal
54
B33
I
TMDS data (negative) input terminal Not used
55
A33
I
TMDS data (positive) input terminal Not used
56
VCC
-
Power supply terminal (+3.3V)
57
B34
I
TMDS data (negative) input terminal Not used
58
A34
I
TMDS data (positive) input terminal Not used
59
GND
-
Ground terminal
60
NC
-
Not used
61
VCC
-
Power supply terminal (+3.3V)
62
HPD2
O
Hot plug detection signal output to the HDMI DVD IN jack
63
SDA2
I/O
I2C two-way data bus with the HDMI DVD IN jack
64
SCL2
I
I2C clock signal input from the HDMI DVD IN jack
65
GND
-
Ground terminal
66
B21
I
TMDS clock signal (negative) input from the HDMI DVD IN jack
67
A21
I
TMDS clock signal (positive) input from the HDMI DVD IN jack
68
VCC
-
Power supply terminal (+3.3V)
69
B22
I
TMDS data (negative) input from the HDMI DVD IN jack
70
A22
I
TMDS data (positive) input from the HDMI DVD IN jack
71
GND
-
Ground terminal
72
B23
I
TMDS data (negative) input from the HDMI DVD IN jack
73
A23
I
TMDS data (positive) input from the HDMI DVD IN jack
74
VCC
-
Power supply terminal (+3.3V)
75
B24
I
TMDS data (negative) input from the HDMI DVD IN jack
76
A24
I
TMDS data (positive) input from the HDMI DVD IN jack
77
GND
-
Ground terminal
78
NC
-
Not used
79
VCC
-
Power supply terminal (+3.3V)
80
HPD1
O
Hot plug detection signal output to the HDMI VIDEO 2/BD IN jack
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