Sony HTP-78SS / HT-SF1100 / HT-SS1100 / STR-KS1100 Service Manual ▷ View online
41
STR-KS1100
•
IC Pin Function Description
MAIN BOARD IC1501 CXD9862R (DIGITAL AUDIO SIGNAL PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
VSS
-
Ground terminal
2
XRST
I
System reset signal input from the system controller "L": reset
3
EXTIN
I
Master clock signal input terminal Not used
4
LRCKI3
I
L/R sampling clock signal input terminal Not used
5
VDDI
-
Power supply terminal (+1.8V)
6
BCKI3
I
Bit clock signal input terminal Not used
7
PLOCK
O
PLL lock signal output terminal Not used
8
VSS
-
Ground terminal
9
MCLK1
I
System clock input terminal (13.9 MHz)
10
VDDI
-
Power supply terminal (+1.8V)
11
VSS
-
Ground terminal
12
MCLK2
O
System clock output terminal (13.9 MHz)
13
MS
I
Master/slave selection signal input terminal "L": internal clock, "H": external clock
Fixed at "L" in this set
Fixed at "L" in this set
14
SCKOUT
O
Master clock signal output to the stream processor
15
LRCKI1
I
L/R sampling clock signal input from the digital audio interface receiver
16
VDDE
-
Power supply terminal (+3.3V)
17
BCKI1
I
Bit clock signal input from the digital audio interface receiver
18
SDI1
I
Audio serial data input from the A/D converter
19
LRCKO
O
L/R sampling clock signal output to the stream processor
20
BCKO
O
Bit clock signal output to the stream processor
21
VSS
-
Ground terminal
22
KFSIO
I
Audio clock signal input from the digital audio interface receiver
23 to 25
SDO1 to SDO3
O
Audio serial data output to the stream processor
26
SDO4
O
Audio serial data output terminal Not used
27
SPDIF
O
SPDIF signal output terminal Not used
28
LRCKI2
I
L/R sampling clock signal input from the digital audio interface receiver
29
BCKI2
I
Bit clock signal input from the digital audio interface receiver
30
SDI2
I
Audio serial data input from the digital audio interface receiver
31
VSS
-
Ground terminal
32
HACN
O
Acknowledge signal output to the system controller
33
HDIN
I
Serial data input from the system controller
34
HCLK
I
Serial data transfer clock signal input from the system controller
35
HDOUT
O
Serial data output to the system controller
36
HCS
I
Chip select input from the system controller
37
GP12
I
Write enable signal input from the system controller
38
GP13
O
SD-RAM chip enable output terminal Not used
39
GP14
O
Row address strobe signal output terminal Not used
40
VDDI
-
Power supply terminal (+1.8V)
41
VSS
-
Ground terminal
42
GP15
O
Column address strobe signal output terminal Not used
43
OE0
O
Output enable signal output to the S-RAM
44
CS0
O
Chip select signal output to the S-RAM
45
WE0
O
Write enable signal output to the S-RAM
46
VDDE
-
Power supply terminal (+3.3V)
47
WMD1
I
External memory wait mode setting terminal Fixed at "H" in this set
42
STR-KS1100
Pin No.
Pin Name
I/O
Description
48
VSS
-
Ground terminal
49
WMD0
I
External memory wait mode setting terminal Fixed at "H" in this set
50
PAGE2
O
External memory page selection signal output terminal Not used
51
VSS
-
Ground terminal
52, 53
PAGE1, PAGE0
O
External memory page selection signal output terminal Not used
54
BOOT
I
Boot mode control signal input terminal Not used
55
TST1
O
Output terminal for the test Not used
56
BST
I
Boot strap signal input from the system controller
57
MOD1
I
Operation mode setting terminal "L": enhanced mode, "H": normal mode
Fixed at "H" in this set
Fixed at "H" in this set
58
MOD0
I
Operation mode setting terminal "L": single chip mode, "H": can not use
Fixed at "L" in this set
Fixed at "L" in this set
59
EXLOCK
I
PLL lock error signal and data error flag input from the digital audio interface receiver
60
VDDI
-
Power supply terminal (+1.8V)
61
VSS
-
Ground terminal
62, 63
A17, A16
O
Address signal output terminal Not used
64 to 66
A15 to A13
O
Address signal output to the S-RAM
67
GP10
I
L/R sampling clock signal input terminal
68
GP9
O
Read ready signal output to the system controller
69
GP8
I
PCM audio data input from the digital audio interface receiver
70
VDDI
-
Power supply terminal (+1.8V)
71
VSS
-
Ground terminal
72 to 75
D15 to D12
I/O
Two-way data bus with the S-RAM
76
VDDE
-
Power supply terminal (+3.3V)
77 to 80
D11 to D8
I/O
Two-way data bus with the S-RAM
81
VSS
-
Ground terminal
82 to 85
A9, A12 to A10
O
Address signal output to the S-RAM
86
TDO
O
Simplicity emulation data output terminal Not used
87
TMS
I
Simplicity emulation data input start and end terminal Not used
88
XTRST
I
Simplicity emulation non-sync break signal input terminal Not used
89
TCK
I
Simplicity emulation clock signal input terminal Not used
90
TDI
I
Simplicity emulation data input terminal Not used
91
VSS
-
Ground terminal
92 to 97
A8 to A3
O
Address signal output to the S-RAM
98, 99
D7, D6
I/O
Two-way data bus with the S-RAM
100
VDDI
-
Power supply terminal (+1.8V)
101
VSS
-
Ground terminal
102 to 105
D5 to D2
I/O
Two-way data bus with the S-RAM
106
VDDE
-
Power supply terminal (+3.3V)
107, 108
D1, D0
I/O
Two-way data bus with the S-RAM
109, 110
A2, A1
O
Address signal output to the S-RAM
111
VSS
-
Ground terminal
112
A0
O
Address signal output to the S-RAM
113
PM
I
PLL initialize signal input from the system controller
114, 115
SDI3, SDI4
I
Audio serial data input terminal Not used
116
SYNC
I
Sync/non-sync setting terminal "L": sync, "H": non-sync Fixed at "H" in this set
117
TST2
O
Output terminal for the test Not used
118
GP11
-
Not used
43
STR-KS1100
Pin No.
Pin Name
I/O
Description
119
TST3
O
Output terminal for the test Not used
120
VDDI
-
Power supply terminal (+1.8V)
44
STR-KS1100
MAIN BOARD IC1601 MB90F045PF-G-9036-SPE1 (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
DATA0
I
Audio serial data input from the digital audio interface receiver
2
GP9
I
Read ready signal input from the digital audio signal processor
3
BST
O
Boot strap signal output to the digital audio signal processor
4
HCS
O
Chip select signal output to the digital audio signal processor
5
HACN
I
Acknowledge signal input from the digital audio signal processor
6
XRST
O
System reset signal output to the digital audio signal processor "L": reset
7
PM
O
PLL initialize signal output to the digital audio signal processor
8
PWM_DA
O
Power on/off control signal output terminal Not used
9
GP12
O
Write enable signal output to the digital audio signal processor
10
AD_RST
O
System reset signal output to the A/D converter "L": reset
11
VSS
-
Ground terminal
12
HDMI-SW1
O
Source selection signal output to the HDMI receiver/transceiver and analog switch
13
HDMI-DET
I
HDMI jack detection signal input terminal
14
HDMI-OEB
O
Chip enable signal output to the HDMI receiver/transceiver
15
HDMIPRE
-
Not used
16
HDMI-CTL
O
Power on/off control signal output terminal for the HDMI section "H": power on
17
P-CONT2
O
Power on/off control signal output terminal "H": power on
18
HDOUT
I
Serial data input from the digital audio signal processor
19
HDIN
O
Serial data output to the digital audio signal processor
20
HCLK
O
Serial data transfer clock signal output to the digital audio signal processor
21
BD3842 DATA
O
Serial data output to the analog audio input selector
22
BD3842 CLK
O
Serial data transfer clock signal output to the analog audio input selector
23
VCC5
-
Power supply terminal (+3.3V)
24, 25
NO USE
-
Not used
26
POWER_SD
I
Shut down signal input from the digital power amplifier "L": shut down
27
FLASH2/
C_LINK_RX
I
Receive data input from the DMPORT connector
28
FLASH1/
C_LINK_TX
O
Transmit data output to the DMPORT connector
29
C_LINK-DEC
I
Digital media port adapter connection detection signal input terminal
30, 31
NO USE
-
Not used
32
POWER_RST
O
System reset signal output to the digital power amplifier "L": reset
33
SCL
O
Serial data transfer clock signal output to the EEPROM
34
SDA
I/O
Two-way data bus with the EEPROM
35
AVCC
-
Power supply terminal (+3.3V)
36
AVRH
I
Reference voltage (+3.3V) input terminal
37
AVSS
-
Ground terminal
38 to 40
A/D0 to A/D2
I
Front panel key input terminal (A/D input)
41
NO USE
-
Not used
42
VSS
-
Ground terminal
43
RDS SIGNAL
I
RDS signal input from the tuner (FM/AM)
44
ADCC2
I
Auto digital cinema calibration microphone signal input terminal
45
VERSION
I
Setting terminal for the destination
46
P.CONT1
O
Power on/off control signal output terminal "H": power on
47
FUSE DETECT
I
Fuse detection signal input terminal Not used
48
STOP P.STOP
I
AC off detection signal input terminal "L": AC off
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