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54

SBSY

O

Subcode block sync signal output to the system controller

55

SBOK/FOK

O

Not used in this set. (Open)

56

IPF

O

Not used in this set. (Open)

57

SFSY/LOCK

O

Not used in this set. (Open)

58

ZDET

O

Zero detection signal output Not used in this set. (Open)

59

GPIN

I

Fixed at “L” in this set.

60

MS

I

Microcomputer interface mode selection signal input    Fixed at “H” in this set.

61

DOUT (PO6)

O

Digital audio data output    Not used in this set. (Open)

62

AOUT1 (PO7)

O

Audio data output    Not used in this set. (Open)

63

BCK (PO8)

O

Bit clock signal output to the USB controller

64

LRCK (PO9)

O

L/R sampling clock signal output

65

AIN (PI4)

I

Digital audio data input from the USB controller

66

BCKi (PI5)

I

Bit clock signal input from the USB controller

67

LRCKi (PI6)

I

L/R sampling clock signal input from the USB controller

68

VDD1

—

Power supply pin (+1.5 V)

69

VSS

—

Ground pin

70

AWRC

—

Not used in this set. (Open)

71

PVDD3

—

Power supply pin (+3.3 V)

72

PDO

O

Phase error margin signal between EFM signal and PLCK signal output

73

TMAXS

O

TMAX detection signal output Not used in this set. (Open)

74

TMAX

O

TMAX detection signal output

75

LPFN

I

Inverted signal input from the operation amplifi er for PLL loop fi lter

76

LPFo

O

Signal output from the operation amplifi er for PLL loop fi lter

77

PVREF

I

Reference voltage (+1.65 V) input

78

VCOF

O

VCO fi lter output

79

PVSS3

—

Ground pin

80

SLCo

O

EFM slice level output

81

RFi

I

RF signal input

82

RFRPi

I

RF ripple signal input

83

RFEQo

O

EFM slice level output

84

VRo

O

Reference voltage (+1.65 V) output

85

RESiN

O

External resistor connection pin

86

VMDiR

O

Reference voltage (+1.65 V) output for automatic power control circuit

87

TESTR

O

Low-pass fi lter terminal for RFEQO offset correction

88

AGCi

I

RF signal amplitude adjustment amplifi cation input

89

RFo

O

RF signal generation amplifi cation output

90

RVDD3

—

Power supply pin (+3.3 V)

91

LDo

O

Laser diode on/off control signal output to the automatic power control circuit
“H”: laser diode on

92

MDi

I

Light amount monitor input from the laser diode of optical pick-up block

93

RVSS3

—

Ground pin

94

FNi2 (C)

I

Main beam (C) input from the optical pick-up block

95

FNi1 (A)

I

Main beam (A) input from the optical pick-up block

96

FPi2 (D)

I

Main beam (D) input from the optical pick-up block

97

FPi1 (B)

I

Main beam (B) input from the optical pick-up block

98

TPi (F)

I

Sub beam (F) input from the optical pick-up block

99

TNPC

O

External capacitor connection pin

100

TNi (E)

I

Sub beam (E) input from the optical pick-up block

1

RESET

I

Reset signal input from the system controller “L”: reset

2

PC0/INT0

I

Ready to send signal input from the system controller

3

PC1/INT1

O

Not used in this set.    Connected to ground.

4

PC2/INT2/TB1IN0

O

Not used in this set.    Connected to ground.

5

PC3/INT3

I

Function selection signal input    Fixed at “L” in this set.

6

DVCC3B

—

Power supply pin (+3.3 V)

7

PC6/XT1

O

Not used in this set. (Open)

8

PC7/XT2

O

Not used in this set. (Open)

9

PWE

O

Not used in this set. (Open)

10

DVSS1B

—

Ground pin

11

DVCC1B

—

Power supply pin (+3.3 V)

12

RVOUT1

O

Reference voltage (+3.3 V) output pin

13, 14

RVIN

I

Reference voltage (+3.3 V) input pin

15

RVOUT2

O

Reference voltage (+3.3 V) output pin

16

DVCC1A

—

Power supply pin (+3.3 V)

17

DVSS1A

—

Ground pin

18 to 25

P00/D0 to P07/D7

I/O

Two-way data bus with the S-RAM

26

DVSS

—

Ground pin

27

DVCC3A

—

Power supply pin (+3.3 V)

28 to 35

P10/D8 to P17/D15

I/O

Two-way data bus with the S-RAM

36

P40/A0

O

Address signal output pin Not used in this set. (Open)

37 to 43

P41/A1 to P47/A7

O

Address signal output to the S-RAM

44

DVSS

—

Ground pin

45

DVCC3A

—

Power supply pin (+3.3 V)

46 to 54

P50/A8 to P60/A16

O

Address signal output to the S-RAM

55 to 58

P61/A17 to P64/A20

O

Serial data output to the CD-MP3 processor

59

P65/A21

O

Serial data transfer clock signal output to the CD-MP3 processor

60

P66/A22

O

Chip enable signal output to the CD-MP3 processor

61

P67/A23

O

Not used in this set. (Open)

62

DVSS

—

Ground pin

63

DVCC3A

—

Power supply pin (+3.3 V)

64

P70/RD

O

Output enable signal output to the S-RAM

65

P71/SRWR

O

Write enable signal output to the S-RAM

66

P72/SRLLB

O

Lower-byte control signal output to the S-RAM

67

P73/SRLUB

O

Upper-byte control signal output to the S-RAM

68

P74/TA0IN

O

Not used in this set. (Open)

69

P80/CS0/TA1OUT (BOOT)

I

Boot mode selection signal input “L”: boot mode

70

P82/CS2

I

Chip select signal output to the S-RAM

71

P83/CS3/WAIT/TA5OUT

O

L/R sampling clock signal output to the CD-MP3 processor

72

AM1

I

Function mode selection signal input    Fixed at “H” in this set.

73

X2

O

System clock output (9 MHz)

74

DVSS

—

Ground pin

75

X1

I

System clock input (9 MHz)

76

DVCC3A

—

Power supply pin (+3.3 V)

77

P75/USBOC

I

Over current detection signal input

78

P76/USBPON

O

USB VBUS power on/off control signal output “H”: power on

79

D+

I/O

Two-way data (positive) bus with the USB connector

80

D–

I/O

Two-way data (negative) bus with the USB connector

81

AM0

I

Function mode selection signal input    Fixed at “H” in this set.

82

P77/X1USB

O

Not used in this set. (Open)

83

DVSS

—

Ground pin

84

PF0/TXD0

O

Clear to send signal output to the system controller

85

PF1/RXD0

O

Serial data signal output

86

PF2/SCLK0/CTS0/

CLK/TB0OUT0

O

Serial data transfer clock signal output

87

PF3/TXD1/SPDO

O

Serial data signal output to the system controller

88

PF4/RXD1/SPDI

I

Serial data signal input from the system controller

89

PF5/SCLK1/CTS1/SPCLK

O

Not used in this set. (Open)

90

PN1/SDA0/TA3OUT/SO0

I/O

Two-way EEPROM IIC data bus Not used in this set.

91

PN2/SCL0/TA2IN/SI0

I/O

Two-way EEPROM IIC clock bus Not used in this set.

92

PN3/HCLK

O

Bit clock signal output to the CD-MP3 processor

93

PN4/HSSO/SDA1

O

Audio data output to the CD-MP3 processor

94

PN5/HSSI/SCL1

O

Gate signal output to the CD-MP3 processor

95

DVCC3A

—

Power supply pin (+3.3 V)

96

PG

I

Request signal input from the CD-MP3 processor

97

PG

I

Request signal input from the CD-MP3 processor

98, 99

PG1, PG0

I

Function selection signal input    Fixed at “L” in this set.

100

DVSS

—

Ground pin

NOTE:
•  The mechanical parts with no reference 
   number in the exploded views are not 
 supplied.
•  Items marked “*” are not stocked since 
  they are seldom required for routine service. 
  Some delay should be anticipated 
  when ordering these items.

•  -XX and -X mean standardized parts, so 
  they may have some difference from the 
 original one.
•  Accessories are given in the last of this
 parts list.

The components identifi ed by
mark 

0 or dotted line with mark 

0 are critical for safety.
Replace only with part number
specifi ed.

#1

#1

#1

front panel section (1)

chassis section

#1

 

1 

3-363-099-32 

SCREW (CASE 3 TP2)

 2 

3-363-099-02  SCREW 

(CASE 

3 

TP2)

 3 

3-703-136-12  SCREW, 

TAPPING

 4 

2-342-117-51  CASE 

(TOP) 

 5 

3-285-301-51  PANEL, 

LOADING

 6 

3-077-331-21  +BV3 

(3-CR)

 7 

3-285-328-11  PANEL, 

SIDE-R

 8 

3-285-327-11  PANEL, 

SIDE-L

  #1 

7-685-647-79 

SCREW +BVTP 3X10 TYPE2 IT-3

Ref. No. 

Part No. 

Description 

Remark