Sony HCD-CPX11 Service Manual ▷ View online
53
HCD-CPX11
Pin No.
Pin Name
I/O
Description
94
IOVSS0
—
I/O digital ground
95
XTACN
I
Oscillation circuit control
Self-oscillation when high, oscillation stop when low
96
SQSO
O
Subcode Q 80-bit and PCM peak and level data output
CD TEXT data output
97
SQCK
I
SQSO readout clock input
98
SBSO
O
Subcode P to W serial output
99
EXCK
I
SBSO readout clock input
100
XRST
I
System reset Reset when low
101
SYSM
I
Mute input Muted when high
102
D ATA
I
Serial data input from CPU
103
VSS
—
Internal digital ground
104
XLAT
I
Latch input from CPU The serial data is latched at the falling edge
105
CLOCK
I
Serial data transfer clock input from CPU
106
VDD
—
Internal digital power supply
107
SENS
O
SENS output to CPU
108
SCLK
I
SENS serial data readout clock input
109
ATSK
I/O
Anti-shock input/output (Not used)
110
WFCK
O
WFCK output (Not used)
111
XUGF
O
XUGF output (Not used)
112
XPCK
O
XPCK output (Not used)
113
GFS
O
GFS output (Not used)
114
C2PO
O
C2PO output (Not used)
115
SCOR
O
High output when the subcode sync, S0 or S1, is detected
116
VDD
—
Internal digital power supply
117
C4M
O
4 2336MHz output (Not used)
118
WDCK
O
Word clock output f = 2Fs (Not used)
119
COUT
I/O
Track number count signal input/output (Not used)
120
NC
—
Not used
54
HCD-CPX11
• MAIN BOARD IC300 M3062CMEN-A14FPU0 (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
MILP
O
CS signal output to the digital signal processor
2
MP3 REQ
I
REQ output to CD digital processor signal output
3
MIACK
I
ACK input from CD digital processor input
4
SIRCS IN/WAKE
I
Remote control signal input terminal
5
MP3 DATA OUT
O
Serial data output to MP3
6
MP3 DATA IN
I
Serial data input from MP3
7
MP3 CLK
O
Serial data transfersignal output to MP3
8
BYTE
—
Not used
9
CNVSS
—
Ground terminal
10
XCIN
I
Sub system clock input terminal (32.768 kHz)
11
XCOUT
O
Sub system clock output terminal (32.768 kHz)
System reset signal input from the reset signal generator “L”: reset
12
RESET
I
For several hundreds msec. after the power supply rises, “L” is input,
then it changes to “H”
13
XOUT
O
Main system clock output terminal (16 MHz)
14
VSS
—
Ground terminal
15
XIN
I
Main system clock input terminal (16 MHz)
16
VCC
—
Power supply terminal (+3.3V)
17
NMI
I
Non-maskable interrupt input terminal Not used
18
RDS CLK
I
Serial data transfer clock signal input from the RDS decoder Not used
19
CD SCOR
I
Subcode sync (S0+S1) detection signal input from the digital signal processor
20
AC CUT
I
AC off detection signal input from the reset signal generator “L”: AC cut checked
21
MP3 RST
O
RESET output to CD digital processor
22
MICS
O
CS output to the CD digital processor
23
MP3 STB
O
MP3 STB output signal
24
CDM LOAD-IN
O
Motor drive signal (close direction) output terminal
25
CDM LOAD-OUT
O
Motor drive signal (open direction) output terminal
26
CDM SW3
I
Loading in/out detect switch input terminal “L”: loading in
27
CDM SW1
I
Loading in/out detect switch input terminal “L”: loading in
28
CDM SW2
I
Loading in/out detect switch input terminal “L”: loading in
29
IIC CLK
I/O
Communication data transfer clock signal input/output terminal Not used
30
IIC DATA
I/O
Communication data bus terminal Not used
31
NO USE
—
Not used
32
CD SENS
I
Internal status detection monitor input from the digital signal processor
33
CD XRST
O
Reset signal output to the digital signal processor and motor/coil driver “L”: reset
34
CD XTCN
O
CD XTCN signal output
35
CD DATA
O
Serial data output to the digital signal processor
36
CD XLT
O
Serial data latch pulse signal output to the digital signal processor
37
CD CLK
O
Serial data transfer clock signal output to the digital signal processor
38
CD BD-PWR
O
Power supply on/off control signal output for the CD section “H”: power on
39
PWR RELAY
O
Main system power supply on/off control signal output terminal “H”: power on
40
DIAG
I
Protect signal input from the power amplifier and protect detect circuit
41
ENA
O
Output enable control signal output to the power amplifier
42
SC DT
O
Serial data output to the digital audio signal processor
43
SC SHIFT
O
Serial data shift clock signal output to the digital audio signal processor
44
SC LATCH
O
Serial data latch pulse signal output to the digital audio signal processor
55
HCD-CPX11
Pin No.
Pin Name
I/O
Description
45
NSP MUTE
O
Muting on/off control signal output to the digital audio signal processor
“L”: muting on
46
INIT
O
Reset signal output to the digital audio signal processor “L”: reset
47
ST CLK
O
PLL serial data transfer clock signal output to the tuner unit
48
ST DATA IN
I
PLL serial data input from the tuner unit
49
ST DATA OUT
O
PLL serial data output to the tuner unit
50
ST CE
O
PLL chip enable signal output to the tuner unit
51
ST TUNED
I
Tuning detection signal input from the tuner unit “L”: tuned
52
ST STEREO
I
FM stereo detection signal input from the tuner unit “L”: stereo
53
ST MUTE
O
Tuner muting on/off control signal output to the tuner unit “H”: muting on
54
RDS DATA
I
Serial data input from the RDS decoder
55
EQ CLK
O
Serial data transfer clock signal output to the electrical volume
56
NO USE
—
Not used
57
EQ CE
O
Chip enable signal output to the electrical volume
58
HP MUTE
O
Headphone muting on/off control signal output terminal “H”: muting on
59
LINE MUTE
O
Audio line muting on/off control signal output terminal “H”: muting on
60
CD MUTE
O
CD analog signal muting on/off control signal output terminal “H”: muting on
61
TC ALC
O
Automatic limiter control signal output to the recording/playback equalizer
amplifier “H”: limiter on
62
VCC
—
Power supply terminal (+3.3V)
63
SOFT TEST
O
Output terminal for the software test Not used
64
VSS
—
Ground terminal
65
TC REC/MUTE
O
Recording muting on/off control signal output to the recording/playback equalizer
amplifier “L”: muting on
66
TC LINE MUTE
O
Line muting on/off control signal output to the recording/playback equalizer
amplifier “H”: muting on
67
TC PB/REC
O
Recording/playback selection signal output terminal “L”: playback, “H”: recording
68
TC BIAS-ON
O
Recording bias on/off control signal output terminal “H”: bias on
69
TC PLAY SW
I
Head position detect switch input terminal
70
TC CAPM-CONT
O
Capstan/reel motor on/off control signal output terminal “H”: motor on
71
TC TRG
O
Trigger plunger on/off control signal output terminal “H”: plunger on
72
LCD INH
O
Reset signal output to the liquid crystal display driver “L”: reset
73
LCD MODE
O
Signal output for discriminating between command and display data to the liquid
crystal display driver “L”: display data, “H”: command
74
KEY WAKE UP
I
System wake up signal input by pressing any key
75
LCD DATA/EQ DATA
O
Serial data output to the liquid crystal display driver
76
LCD SCL
O
Serial data transfer clock signal output to the liquid crystal display driver
77
LCD CE
O
Chip select signal output to the liquid crystal display driver “L” active
78
LCD ON/LCD BL
O
Power on/off control signal output for liquid crystal display “H”: power on
79
LED TC
O
LED drive signal output of the TAPE
nN
indicator “H”: LED on
80
LED TUNER
O
LED drive signal output of the TUNER BAND indicator “H”: LED on
81
LED STANDBY
O
LED drive signal output of the standby indicator “H”: LED on
82
LED DSG
O
LED drive signal output of the DSG indicator “H”: LED on
83
TRE A
I
Jog dial pulse input from the rotary encoder (TREBLE) (A phase input)
84
TRE B
I
Jog dial pulse input from the rotary encoder (TREBLE) (B phase input)
85
BASS A
I
Jog dial pulse input from the rotary encoder (BASS) (A phase input)
56
HCD-CPX11
Pin No.
Pin Name
I/O
Description
86
BASS B
I
Jog dial pulse input from the rotary encoder (BASS) (B phase input)
87
VOL A
I
Jog dial pulse input from the rotary encoder (VOLUME) (A phase input)
88
VOL B
I
Jog dial pulse input from the rotary encoder (VOLUME) (B phase input)
89
LED CD
O
LED drive signal output of the CD
NX
indicator “H”: LED on
90
TC END SW
I
Tape end detect switch input terminal
91
TC HALF/REC/SW
I
Recording-proof claw (forward/reverse) detect switch and cassette in detect
switch input terminal (A/D input)
92
MODEL
I
Model setting terminal
93
DEST
I
Destination setting terminal
94, 95
KEY3, KEY2
I
Front panel key input terminal (A/D input)
96
AVSS
—
Ground terminal (for analog system)
97
KEY1
I
Front panel key input terminal (A/D input)
98
VREF
I
Reference voltage (+3.3V) input terminal
99
AVCC
—
Power supply terminal (+3.3V) (for analog system)
100
HP DET
I
Headphone jack connection detection signal input terminal
“L”: no connected, “H”: headphone connected
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