Sony HCD-CPX11 Service Manual ▷ View online
49
HCD-CPX11
IC650, 680
CXD9750L
CROSS OVER
DELAY
FILTER
THERMAL
SHUT DOWN
UNDER
VOLTAGE
LOCK–OUT
HIGH SIDE
LEVEL SHIFT
PROTECTOR
CIRCUIT
PRE
DRIVER
LOW SIDE
LEVEL SHIFT
PRE
DRIVER
-
16
INB
15
GNDB
14
VDDB
20
SB
19
OUTB
13
VDRVB
12
VBOOTB
11
VBBB
VDRVB
VBBB
17
ENB
18
DIAGB
CROSS OVER
DELAY
THERMAL
SHUT DOWN
UNDER
VOLTAGE
LOCK–OUT
HIGH SIDE
LEVEL SHIFT
PROTECTOR
CIRCUIT
PRE
DRIVER
LOW SIDE
LEVEL SHIFT
PRE
DRIVER
6
INA
5
GNDA
4
VDDA
10
SA
9
OUTA
3
VDRVA
2
VBOOTA
1
VBBA
VDRVA
VBBA
7
ENA
8
DIAGA
VDRVA
VDRVB
VBBA
VBBB
VBBB
+
FILTER
+
-
-
VBBA
+
+ -
50
HCD-CPX11
– LCD Board –
SINGLE-END/
DIFFERENTIAL
CONVERTER
5TH ORDER
DELTA-SIGMA
MODULATOR
VINL
1
SINGLE-END/
DIFFERENTIAL
CONVERTER
VINR
2
VREF1
3
VREF2
4
5TH ORDER
DELTA-SIGMA
MODULATOR
REFERENCE
x16 1/64
(x1/128)
DECIMATION
FILTER
WITH
DC CUT
FILTER
SERIAL
INTERFACE
&
MODE/FORMAT
CONTROL
MODE1
20
MODE0
19
FMT1
18
FMT0
17
DOUT
12
BCK
11
OSR
16
SCKI
15
VDD
14
DGND
13
CLOCK & TIMING CONTROL
PDWN
7
BYPAS
8
VCC
5
AGND
6
FSYNC
9
LRCK 10
POWER
SUPPLY
IC603
PCM1802DBR
49
50
16 - 1
33 - 48
17 - 32
51
52
53
54
55
56
57
58
59
60
61
62
63
64
SEG1 - 16
SEG33 - 48
SEG49
SEG50
OSC1
OSC2
VDD
VSS
VLCD
CE
SCL
DATA
MODE
INH
COM4
COM3
COM2
COM1
SEG17 - 32
Latch Circuit / Segment Driver
Common
Driver
Input Select Circuit
Input
Select
Shift
Register3
50-Bit
Oscillation
Circuit
Dividing
Circuit
Input
Select
Shift
Register4
50-Bit
Input
Select
Shift
Register2
50-Bit
Input
Select
Shift
Register1
50-Bit
Decoder
Shift Register
Control Circuit
IC801
NJU6433F
51
HCD-CPX11
6-16. IC PIN FUNCTION DESCRIPTION
• BD81A BOARD IC101 CXD3059AR (RF AMP)
Pin No.
Pin Name
I/O
Description
1
MIRR
I/O
Mirror signal input/output (Not used)
2
DFCT
I/O
Defect signal input/output (Not used)
3
FOK
I/O
Focus OK signal input/output (Not used)
4
VSS
—
Internal digital ground
5
LOCK
I/O
GFS is sampled at 460Hz; when GFS is high , this pin outputs a high signal
If GFS is low eight consecutive
6
MDP
O
Spindle motor servo control output
7
SSTP
I
Disk innermost detection signal input
8
IOVSS1
—
I/O digital ground
9
SFDR
O
Sled drive output
10
SRDR
O
Sled drive output
11
TFDR
O
Tracking drive output
12
TRDR
O
Tracking drive output
13
FFDR
O
Focus drive output
14
FRDR
O
Focus drive output
15
IOVDD1
—
I/O digital power supply
16
AVDD0
—
Analog power supply
17
AVSS0
—
Analog ground
18
NC
—
Not used
19
E
I
E signal input
20
F
I
F signal input
21
TEI
I
Tracking error signal input to DSSP block
22
TEO
O
Tracking error signal output from RF amplifier block
23
FEI
I
Focus error signal input to DSSP block
24
FEO
O
Focus error signal output from RF amplifier block
25
VC
I/O
Center voltage output from RF amplifier block
26
A
I
A signal input
27
B
I
B signal input
28
C
I
C signal input
29
D
I
D signal input
30
NC
—
Not used
31
AVDD4
—
Analog power supply
32
RFDCO
O
RFDC signal output (Not used)
33
PDSENS
I
Reference voltage pin for PD
34
AC_SUM
O
RFAC summing amplifier output
35
EQ_IN
I
Equalizer circuit input
36
LD
O
APC amplifier output
37
PD
I
APC amplifier input
38
NC
—
Not used
39
RFC
I
Equalizer cut-off frequency adjustment pin
40
AVSS4
—
Analog ground
41
RFACO
O
RFAC signal output
42
RFACI
I
RFAC signal input or EFM signal input
43
AVDD3
—
Analog power supply
44
BIAS
I
Asymmetry circuit constant current input
45
ASYI
I
Asymmetry comparator voltage input
46
ASYO
O
EFM full-swing output (Low = VSS, High = VDD)
52
HCD-CPX11
Pin No.
Pin Name
I/O
Description
47
VPCO
O
Wide-band EFM PLL charge pump output (Not used)
48
VCTL
I
Wide-band EFM PLL VCO2 control voltage input
49
AVSS3
—
Analog ground
50
CLTV
I
Multiplier VCO1 control voltage input
51
FILO
O
Master PLL (slave = digital PLL) filter output
52
FILI
I
Master PLL filter input
53
PCO
O
Master PLL charge pump output
54
AVDD5
—
Analog power supply
55
DDVROUT
O
DC/DC converter output
56
DDVRSEN
I
DC/DC converter output voltage monitor pin
57
AVSS5
—
Analog ground
58
DDCR
I
DC/DC converter reset pin
59
NC
—
Not used
60
BCKI
I
D/A interface bit clock input
61
PCMDI
I
D/A interface serial data input (2’s COMP, MSB first)
62
LRCKl
I
D/A interface LR clock input
63
LRCK
O
D/A interface LR clock output f = Fs
64
VSS
—
Internal digital ground
65
PCMD
O
D/A interface serial data output (2’s COMP, MSB first)
66
BCK
O
D/A interface bit clock output
67
VDD
—
Internal digital power supply
68
EMPH
O
High when the playback disc has emphasis, low it has not
69
EMPHI
I
High when de-emphasis is ON, low when input OFF
70
IOVDD2
—
I/O digital power supply
71
DOUT
O
Digital Out output
72
TEST
I
Test pin Normally ground
73
TES1
I
Test pin Normally ground
74
IOVss2
—
I/O digital ground
75
NC
—
Not used
76
XVSS
—
Master clock ground
77
XTAO
O
Crystal oscillation circuit output
78
XTAI
I
Crystal oscillation circuit input
79
XVDD
—
Master clock power supply
80
AVDD1
—
Analog power supply
81
AOUT1
O
Lch analog output
82
VREFL
O
Lch reference voltage
83
AVSS1
—
Analog ground
84
AVSS2
—
Analog ground
85
VREFR
O
Rch reference voltage
86
AOUT2
O
Rch analog output
87
AVDD2
—
Analog power supply
88
NC
—
Not used
89
IOVDD0
—
I/O digital power supply
90
RMUT
O
Rch “0” detection flag (Not used)
91
LMUT
O
Lch “0” detection flag (Not used)
92
NC
—
Not used
93
XTSL
I
Crystal selection input (Not used)
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