Sony HBD-EF1100 Service Manual ▷ View online
HBD-EF1100
69
Pin No.
Pin Name
I/O
Description
E7
DML
I
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM
is sampled HIGH coincident with that input data during a Write access. DM is sampled on
both edges of DQS. For x8 device, the function of DM or TDQS/ TDQS is enabled by Mode
Register A11 setting in MR1.
is sampled HIGH coincident with that input data during a Write access. DM is sampled on
both edges of DQS. For x8 device, the function of DM or TDQS/ TDQS is enabled by Mode
Register A11 setting in MR1.
E8
VSSQ
-
DQ Ground
E9
VDDQ
-
DQ Power Supply: 1.5V +/-0.075V
F1
VDDQ
-
DQ Power Supply: 1.5V +/-0.075V
F2
DQL2
I/O
Data Input/output: Bi-directional data bus.
F3
DQSL
I/O
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, cen-
tered in write data. For the x16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corre-
sponds to the data on DQU0-DQU7. The data strobe DQS, DQSL and DQSU are paired with
differential signals DQS, DQSL and DQSU, respectively, to provide differential pair signaling
to the system during reads and writes. DDR3 SDRAM supports differential data strobe only
and does not support single-ended.
tered in write data. For the x16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corre-
sponds to the data on DQU0-DQU7. The data strobe DQS, DQSL and DQSU are paired with
differential signals DQS, DQSL and DQSU, respectively, to provide differential pair signaling
to the system during reads and writes. DDR3 SDRAM supports differential data strobe only
and does not support single-ended.
F4
NO_USE
-
Not used
F5
NO_USE
-
Not used
F6
NO_USE
-
Not used
F7
DQL1
I/O
Data Input/output: Bi-directional data bus.
F8
DQL3
I/O
Data Input/output: Bi-directional data bus.
F9
VSSQ
-
DQ Ground
G1
VSSQ
-
DQ Ground
G2
DQL6
I/O
Data Input/output: Bi-directional data bus.
G3
DQSL
I/O
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, cen-
tered in write data. For the x16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corre-
sponds to the data on DQU0-DQU7. The data strobe DQS, DQSL and DQSU are paired with
differential signals DQS, DQSL and DQSU, respectively, to provide differential pair signaling
to the system during reads and writes. DDR3 SDRAM supports differential data strobe only
and does not support single-ended.
tered in write data. For the x16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corre-
sponds to the data on DQU0-DQU7. The data strobe DQS, DQSL and DQSU are paired with
differential signals DQS, DQSL and DQSU, respectively, to provide differential pair signaling
to the system during reads and writes. DDR3 SDRAM supports differential data strobe only
and does not support single-ended.
G4
NO_USE
-
Not used
G5
NO_USE
-
Not used
G6
NO_USE
-
Not used
G7
VDD
-
Power Supply: 1.5V +/-0.075
G8
VSS
-
Ground
G9
VSSQ
-
DQ Ground
H1
VREFDQ
-
Reference voltage for DQ
H2
VDDQ
-
DQ Power Supply: 1.5V +/-0.075V
H3
DQL4
I/O
Data Input/output: Bi-directional data bus.
H4
NO_USE
-
Not used
H5
NO_USE
-
Not used
H6
NO_USE
-
Not used
H7
DQL7
I/O
Data Input/output: Bi-directional data bus.
H8
DQL5
I/O
Data Input/output: Bi-directional data bus.
H9
VDDQ
-
DQ Power Supply: 1.5V +/-0.075V
J1
NC
-
No Connect: No internal electrical connection is present.
J2
VSS
-
Ground
J3
RAS
I
Command Input: RAS (along with CS) defi ne the command being entered.
J4
NO_USE
-
Not used
J5
NO_USE
-
Not used
J6
NO_USE
-
Not used
J7
CK
I
Clock: CK is differential clock input. All address and control input signals are sampled on the
crossing of the positive edge of CK. Output (read) data is referenced to the crossing of CK.
crossing of the positive edge of CK. Output (read) data is referenced to the crossing of CK.
J8
VSS
-
Ground
J9
NC
-
No Connect: No internal electrical connection is present.
K1
ODT
I
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the
DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS,
NU/TDQS (When TDQS is enabled via Mode Register A11=1 in MR1) signal for x8 confi gura-
tions. The ODT pin will be ignored if the Mode Register (MR1) is programmed to disable ODT.
DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS,
NU/TDQS (When TDQS is enabled via Mode Register A11=1 in MR1) signal for x8 confi gura-
tions. The ODT pin will be ignored if the Mode Register (MR1) is programmed to disable ODT.
K2
VDD
-
Power Supply: 1.5V +/-0.075
HBD-EF1100
70
Pin No.
Pin Name
I/O
Description
K3
CAS
I
Command Input: CAS (along with CS) defi ne the command being entered.
K4
NO_USE
-
Not used
K5
NO_USE
-
Not used
K6
NO_USE
-
Not used
K7
CK
I
Clock: CK is differential clock input. All address and control input signals are sampled on the
crossing of the negative edge of CK. Output (read) data is referenced to the crossing of CK.
crossing of the negative edge of CK. Output (read) data is referenced to the crossing of CK.
K8
VDD
-
Power Supply: 1.5V +/-0.075
K9
CKE
I
Clock Enable: CKE HIGH activates, and CKE LOW deactivates, internal clock signal and de-
vice input buffers and output drivers. Talking CKE LOW provides Precharge Power-Down and
Self Refresh operation (all banks idle), or Active Power-Down (Row Active in any bank). CKE
is asynchronous for self refresh exit. After V
vice input buffers and output drivers. Talking CKE LOW provides Precharge Power-Down and
Self Refresh operation (all banks idle), or Active Power-Down (Row Active in any bank). CKE
is asynchronous for self refresh exit. After V
REFCA
has become stable during the power on and
initialization sequence, it must be maintained during all operations (including Self-Refresh).
CKE must be maintained high throughout read and write accesses. Input buffers, excluding
CK, CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are
disabled during Self-Refresh.
CKE must be maintained high throughout read and write accesses. Input buffers, excluding
CK, CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are
disabled during Self-Refresh.
L1
NC
-
No Connect: No internal electrical connection is present.
L2
CS
I
Chip Select: All commands are masked when CS is registered HIGH. CS provides for external
Rank selection on system with multiple Ranks. CS is considered part of the command code.
Rank selection on system with multiple Ranks. CS is considered part of the command code.
L3
WE
I
Command Input: WE (along with CS) defi ne the command being entered.
L4
NO_USE
-
Not used
L5
NO_USE
-
Not used
L6
NO_USE
-
Not used
L7
A10
I
Address inputs: Provided the row address for active commands and the column address for
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
Autoprecharge: A10 is sampled during Read/Write commands to determine whether Auto-
precharge should be performed to the accessed bank after the Read/Write operation. (HIGH:
Autoprecharge; LOW: No Autoprecharge)
A10 is sampled during a Precharge command to determine the Percharge applies to one bank
(A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected
by bank adresses.
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
Autoprecharge: A10 is sampled during Read/Write commands to determine whether Auto-
precharge should be performed to the accessed bank after the Read/Write operation. (HIGH:
Autoprecharge; LOW: No Autoprecharge)
A10 is sampled during a Precharge command to determine the Percharge applies to one bank
(A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected
by bank adresses.
L8
ZQ
-
Reference Pin for ZQ calibration
L9
NC
-
No Connect: No internal electrical connection is present.
M1
VSS
-
Ground
M2
BA0
I
Bank Address Inputs: BA0 defi ne to which bank an Active, Read, Write or Precharge com-
mand is being applied. Bank address also determines if the mode register or extended mode
register is to be accessed during a MRS cycle.
mand is being applied. Bank address also determines if the mode register or extended mode
register is to be accessed during a MRS cycle.
M3
BA2
I
Bank Address Inputs: BA2 defi ne to which bank an Active, Read, Write or Precharge com-
mand is being applied. Bank address also determines if the mode register or extended mode
register is to be accessed during a MRS cycle.
mand is being applied. Bank address also determines if the mode register or extended mode
register is to be accessed during a MRS cycle.
M4
NO_USE
-
Not used
M5
NO_USE
-
Not used
M6
NO_USE
-
Not used
M7
NC
-
No Connect: No internal electrical connection is present.
M8
VREFCA
-
Reference voltage for CA
M9
VSS
-
Ground
N1
VDD
-
Power Supply: 1.5V +/-0.075
N2
A3
I
Address inputs: Provided the row address for active commands and the column address for
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
N3
A0
I
Address inputs: Provided the row address for active commands and the column address for
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
N4
NO_USE
-
Not used
N5
NO_USE
-
Not used
N6
NO_USE
-
Not used
N7
A12
I
Address inputs: Provided the row address for active commands and the column address
for Read/Write commands to select one location out of the memory array in the respective
bank. The address inputs also provide the op-code during Mode Register Set commands.
Burst Chop: A12 is sampled during Read and Write commands to determine if burst chop (on-
the-fl y) will be performed. (HIGH: no burst chop, LOW: burst chopped).
for Read/Write commands to select one location out of the memory array in the respective
bank. The address inputs also provide the op-code during Mode Register Set commands.
Burst Chop: A12 is sampled during Read and Write commands to determine if burst chop (on-
the-fl y) will be performed. (HIGH: no burst chop, LOW: burst chopped).
HBD-EF1100
71
Pin No.
Pin Name
I/O
Description
N8
BA1
I
Bank Address Inputs: BA1 defi ne to which bank an Active, Read, Write or Precharge com-
mand is being applied. Bank address also determines if the mode register or extended mode
register is to be accessed during a MRS cycle.
mand is being applied. Bank address also determines if the mode register or extended mode
register is to be accessed during a MRS cycle.
N9
VDD
-
Power Supply: 1.5V +/-0.075
P1
VSS
-
Ground
P2
A5
I
Address inputs: Provided the row address for active commands and the column address for
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
P3
A2
I
Address inputs: Provided the row address for active commands and the column address for
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
P4
NO_USE
-
Not used
P5
NO_USE
-
Not used
P6
NO_USE
-
Not used
P7
A1
I
Address inputs: Provided the row address for active commands and the column address for
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
P8
A4
I
Address inputs: Provided the row address for active commands and the column address for
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
P9
VSS
-
Ground
R1
VDD
-
Power Supply: 1.5V +/-0.075
R2
A7
I
Address inputs: Provided the row address for active commands and the column address for
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
R3
A9
I
Address inputs: Provided the row address for active commands and the column address for
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
R4
NO_USE
-
Not used
R5
NO_USE
-
Not used
R6
NO_USE
-
Not used
R7
A11
I
Address inputs: Provided the row address for active commands and the column address for
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
R8
A6
I
Address inputs: Provided the row address for active commands and the column address for
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
R9
VDD
-
Power Supply: 1.5V +/-0.075
T1
VSS
-
Ground
T2
RESET
I
Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when
RESET is HIGH. RESET must be HIGH during normal operation. RESET is CMOS rail to rail
signal with DC high and low at 80% and 20% of V
RESET is HIGH. RESET must be HIGH during normal operation. RESET is CMOS rail to rail
signal with DC high and low at 80% and 20% of V
DD
, example, 1.20V for DC high and 0.30V
for DC low.
T3
A13
I
Address inputs: Provided the row address for active commands and the column address for
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
T4
NO_USE
-
Not used
T5
NO_USE
-
Not used
T6
NO_USE
-
Not used
T7
NC
-
No Connect: No internal electrical connection is present.
T8
A8
I
Address inputs: Provided the row address for active commands and the column address for
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
T9
VSS
-
Ground
HBD-EF1100
72
MB1002 BOARD (6/6) IC801 R5F3650KCDFB (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
SIRCS_IN
I
SIRCS signal input from the remote control receiver
2
FAN_CONT
O
Fan motor speed control signal output terminal control by DA converter
Port output higher, speed slower
Port output higher, speed slower
3
FL_DOUT
O
Serial data output to the fl uorescent indicator tube driver
4
NO_USE
-
No used
5
FL_CLK
O
Serial data transfer clock signal output to the fl uorescent indicator tube driver
6
BYTE
I
External data bus width selection signal input terminal
7
CNVSS
I
Processor mode selection signal input terminal
8
NFC_SW
O
Stand-by control signal output to the NFC module
9
NFC_IRQ
I
Wireless data reception signal input from NFC module
10
RESET
I
System reset signal input from the reset signal generator and reset switch "L": reset
For several hundreds msec. After the power supply rises, "L" is input, then it change to
"H"
For several hundreds msec. After the power supply rises, "L" is input, then it change to
"H"
11
XOUT
O
System clock output terminal (8MHz)
12
VSS
-
Ground terminal
13
XIN
I
System clock input terminal (5MHz)
14
VCC1
-
Power supply terminal (+3.3V)
15
CEC_TX_RX
I/O
CEC serial data input/output with the HDMI connector
16
NO_USE
-
No used
17
NO_USE
-
No used
18
AC_CUT
I
AC cut detection signal input terminal "L": AC cut
19
NO_USE
-
No used
20
NO_USE
-
No used
21
NO_USE
-
No used
22
NO_USE
-
No used
23
NO_USE
-
No used
24
WHITE_LED
O
Front panel LED drive signal output terminal “H”: on
25
PCONT_FL
O
Power supply on/off control signal output terminal for fl uorescent indicator tube driver
"H": power on
"H": power on
26
BT_LED
O
Bluetooth LED drive signal output terminal “H”: on
27
NO_USE
-
No used
28
NO_USE
-
No used
29
TXD1
O
TXD1 (for debug) / fl ash write TXD1
30
RXD1
I
RXD2 (for debug) / fl ash write RXD1
31
ON CHIP DEBUG / CLK1
I
On chip debuger / fl ash write CLK1
32
NO_USE / RTS1
O
No used
33
TAS5538_SDA
I/O
Two-way data bus with the DAMP processor
34
TAS5538_SCL
I/O
Serial data transfer clock signal output to the DAMP processor
35
DC_DET
I
Speaker DC detection signal input terminal "L": speaker DC is detected
36
PCONT1
O
Power supply on/off control signal output terminal "H": power on
37
PCONT2
O
Power supply on/off control signal output terminal “H”: power on
38
PCONT3
O
Power supply on/off control signal output terminal "H": power on
39
EPM
O
EPM for update used
40
PCONT_STA516
O
STA516 IC Power Control, "H": power on
41
NO_USE
-
No used
42
FAN_ON
O
Power supply on/off control signal output terminal for fan motor "H": power on
43
NO_USE
-
No used
44
CE
I
Chip enable signal input terminal
45
ST_SDA
I/O
Two-way data bus with the FM receiver
46
ST_SCL
I/O
Serial data transfer clock signal output to the FM receiver
47
BD_IF_START
O
Ready signal output to the BD decoder "H": ready
48
TAS5538_XPDN
O
Power down signal output to the power amplifi er "L": power down
49
BD_IF_REQ
I
Request signal input from the BD decoder “H”: request
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