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Model
HBD-EF1100
Pages
88
Size
5.77 MB
Type
PDF
Document
Service Manual
Brand
Device
Audio
File
hbd-ef1100.pdf
Date

Sony HBD-EF1100 Service Manual ▷ View online

HBD-EF1100
65
Pin No.
Pin Name
I/O
Description
P144
RDQ20
I/O
Memory data bit 20
P145
RDQ22
I/O
Memory data bit 22
P146
RDQ18
I/O
Memory data bit 18
P147
DDRVCCIO_8
-
1.5V Digital IO power
P148
RDQ16
I/O
Memory data bit 16
P149
RDQ27
I/O
Memory data bit 27
P150
RDQ25
I/O
Memory data bit 25
P151
RDQ29
I/O
Memory data bit 29
P152
RDQ31
I/O
Memory data bit 31
P153
RDQM3
O
Memory data mask bit 3
P154
DDRVCCK_4
-
1.2V Digital Power
P155
DDRVREF
I
Memory VREF
P156
DDRVCCIO_9
-
1.5V Digital IO Power
P157
RDQS2
I/O
Memory positive data strobe bit 2
P158
RDQS2_
I/O
Memory negative data strobe bit 2
P159
RCLK1_
O
Memory clock 1 negative
P160
RCLK1
O
Memory clock 1 positive
P161
DDRVCCIO_A
-
1.5V Digital IO Power
P162
RDQM2
O
Memory data mask bit 2
P163
RDQS3
I/O
Memory positive data strobe bit 3
P164
RDQS3_
I/O
Memory negative data strobe bit 3
P165
RDQ28
I/O
Memory data bit 28
P166
RDQ30
I/O
Memory data bit 30
P167
RDQ26
I/O
Memory data bit 26
P168
RDQ24
I/O
Memory data bit 24
P169
RDQ17
I/O
Memory data bit 17
P170
DDRVCCIO_B
-
1.5V Digital IO power
P171
RDQ19
I/O
Memory data bit 19
P172
RDQ23
I/O
Memory data bit 23
P173
RDQ21
I/O
Memory data bit 21
P174
DDRVCCK_5
-
1.2V Digital Power
P175
DVCC12_K_5
-
1.2V Digital Power
P176
AVDD33_LDO
-
Line driver 3.3V analog power
P177
AVDD12_LDO
-
1.2 V standby power
P178
OPWRSB
I/O
Power Control
P179
GPIO8
I/O
ICE1_TDO
P180
GPIO7
I/O
ICE1_TCK
P181
GPIO6
I/O
ICE1_TMS
P182
GPIO5
I/O
ICE1_TDI
P183
GPIO4
-
Not used
P184
DVCC33_IO_STB_1
-
3.3V Digital IO Power for Stand-By Module
P185
GPIO3
I/O
WOL_INT
P186
GPIO2
I/O
START_BIT
P187
GPIO1
I/O
XIF_CS
P188
GPIO0
I
IF_SDI
P189
VCLK
-
IF_SCK
P190
VSTB
I
SYS_REQ
P191
VDATA
O
IF_SDO
P192
IR
I
SIRCS
P193
RESET_
I
Power on reset
P194
UATXD
I/O
Reserved for debug-only Uart pins.
(1) 1st RS232 TX
(2) T8032 RS232 TX
HBD-EF1100
66
Pin No.
Pin Name
I/O
Description
P195
UARXD
I/O
Reserved for debug-only Uart pins.
(1) 1st RS232 RX
(2) T8032 RS232 RX
P196
AMUTE
I
UPG_STATUS
P197
HTPLG
I/O
HDMI Hot Plug
P198
DVCC33_IO_STB_2
-
3.3V Digital IO Power for Stand-By Module
P199
HDMISD
I/O
HDMI I2C data
P200
HDMISCK
I/O
HDMI I2C clock
P201
CEC
I/O
HDMI CEC
P202
LED1
I
JIG_MODE0
P203
LED0
I
JIG_MODE1
P204
USB_DM_P2
I/O
USB port2 differential serial data bus (minus)
P205
USB_DP_P2
I/O
USB port2 differential serial data bus (plus)
P206
USB_VRT_P2
-
USB port2 reference resistor
P207
AVDD33_USB_P2
-
3.3V Analog Power for USB port2
P208
AVSS33_BG
-
BG Analog Ground
P209
REXT
O
External reference resistor
P210
AVDD33_COM
-
PLL / BG 3.3 V Analog Power
P211
TXVN_1
I/O
Ethernet RD -
P212
TXVP_1
I/O
Ethernet RD +
P213
TXVN_0
I/O
Ethernet TD -
P214
TXVP_0
I/O
Ethernet TD +
P215
AVDD33_LD
-
3.3 V power for standby
P216
DVCC12_K_6
-
1.2V Digital Power
P217
AVDD33_HDMI
-
3.3 V Analog Power
P218
CLK_M
O
HDMI TX clock differential pair (M)
P219
CLK_P
O
HDMI TX clock differential pair (P)
P220
CH0_M
O
HDMI TX data 0 differential pair (M)
P221
CH0_P
O
HDMI TX data 0 differential pair (P)
P222
CH1_M
O
HDMI TX data 1 differential pair (M)
P223
CH1_P
O
HDMI TX data 1 differential pair (P)
P224
CH2_M
O
HDMI TX data 2 differential pair (M)
P225
CH2_P
O
HDMI TX data 2 differential pair (P)
P226
AVDD12_HDMI_C
-
1.2 V Analog Power
P227
AVDD12_HDMI_D
-
1.2 V Analog Power
P228
AVSS12_HDMI
-
1.2V Analog Ground
P229
NS_XTALI
-
3.3V power for standby
P230
NS_XTALO
I
27MHz Crystal In
P231
AVDD33_PLLGP
-
3.3 V Analog Power for PLL Group
P232
AVDD33_VDAC_BG
-
3.3V Analog Power
P233
AVDD33_VDAC_X
-
3.3V Analog Power
P234
VDACX_OUT
O
DAC output
P235
VMID_PWMDAC
-
PWMDAC internal LDO reference
P236
AVDD33_DAC
-
3.3 V Analog Power
P237
AL0
I
I2S Master Clock line
P238
AVSS33_DAC
-
Analog Ground
P239
AR0
I
I2S Bit Clock line
P240
DVCC33_IO_7
-
3.3V Digital IO power
P241
SPDIF_IN0
I
Microphone signal input
P242
AOLRCK
I/O
Audio output left-right clock
P243
AOSDATA0
I/O
Audio output serial data 0
P244
AOSDATA1
I/O
Audio output serial data 1
P245
AOSDATA2
I/O
Audio output serial data 2
P246
AOSDATA3
I/O
Audio output serial data 3
HBD-EF1100
67
Pin No.
Pin Name
I/O
Description
P247
SPDIF
I/O
SPDIF digital audio output
P248
DVCC12_K_7
-
1.2V Digital Power
P249
AVDD12_1
-
1.2 V Power Pin
P250
RSTI
I
Front-End Power on reset
P251
VDAC0
O
Output of General DAC
P252
VWDC2O
O
Output Voltage 2 of Laser Diode Control in APC
P253
VWDC3O
O
Output Voltage 3 of Laser Diode Control in APC
P254
FVREF
O
Output of Voltage Reference
P255
FPDOCD
I
Laser Power Monitor Input for CD APC / Differential negative input
P256
FPDODVD
I
Laser Power Monitor Input for DVD APC / Differential positive input
P257
EPAD
-
DGND
HBD-EF1100
68
MB1002 BOARD (1/6) IC102, IC103 K4B2G1646E-BCK0  (SD-RAM)
Pin No.
Pin Name
I/O
Description
A1
VDDQ
-
DQ Power Supply: 1.5V +/-0.075V
A2
DQU5
I/O
Data Input/output: Bi-directional data bus.
A3
DQU7
I/O
Data Input/output: Bi-directional data bus.
A4
NO_USE
-
Not used
A5
NO_USE
-
Not used
A6
NO_USE
-
Not used
A7
DQU4
I/O
Data Input/output: Bi-directional data bus.
A8
VDDQ
-
DQ Power Supply: 1.5V +/-0.075V
A9
VSS
-
Ground
B1
VSSQ
-
DQ Ground
B2
VDD
-
Power Supply: 1.5V +/-0.075
B3
VSS
-
Ground
B4
NO_USE
-
Not used
B5
NO_USE
-
Not used
B6
NO_USE
-
Not used
B7
DQSU
I/O
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, cen-
tered in write data. For the x16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corre-
sponds to the data on DQU0-DQU7. The data strobe DQS, DQSL and DQSU are paired with 
differential signals DQS, DQSL and DQSU, respectively, to provide differential pair signaling 
to the system during reads and writes. DDR3 SDRAM supports differential data strobe only 
and does not support single-ended.
B8
DQU6
I/O
Data Input/output: Bi-directional data bus.
B9
VSSQ
-
DQ Ground
C1
VDDQ
-
DQ Power Supply: 1.5V +/-0.075V
C2
DQU3
I/O
Data Input/output: Bi-directional data bus.
C3
DQU1
I/O
Data Input/output: Bi-directional data bus.
C4
NO_USE
-
Not used
C5
NO_USE
-
Not used
C6
NO_USE
-
Not used
C7
DQSU
I/O
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, cen-
tered in write data. For the x16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corre-
sponds to the data on DQU0-DQU7. The data strobe DQS, DQSL and DQSU are paired with 
differential signals DQS, DQSL and DQSU, respectively, to provide differential pair signaling 
to the system during reads and writes. DDR3 SDRAM supports differential data strobe only 
and does not support single-ended.
C8
DQU2
I/O
Data Input/output: Bi-directional data bus.
C9
VDDQ
-
DQ Power Supply: 1.5V +/-0.075V
D1
VSSQ
-
DQ Ground
D2
VDDQ
-
DQ Power Supply: 1.5V +/-0.075V
D3
DMU
I
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM 
is sampled HIGH coincident with that input data during a Write access. DM is sampled on 
both edges of DQS. For x8 device, the function of DM or TDQS/ TDQS is enabled by Mode 
Register A11 setting in MR1.
D4
NO_USE
-
Not used
D5
NO_USE
-
Not used
D6
NO_USE
-
Not used
D7
DQU0
I/O
Data Input/output: Bi-directional data bus.
D8
VSSQ
-
DQ Ground
D9
VDD
-
Power Supply: 1.5V +/-0.075
E1
VSS
-
Ground
E2
VSSQ
-
DQ Ground
E3
DQL0
I/O
Data Input/output: Bi-directional data bus.
E4
NO_USE
-
Not used
E5
NO_USE
-
Not used
E6
NO_USE
-
Not used
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