Sony DVP-S9 / MHC-S9D Service Manual ▷ View online
49
DVP-S9
•
MB BOARD IC103 MB91307APFV-G-BND-E1 (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1 to 5
HA17 to HA21
O
Address signal output terminal
6
HA22
—
Not used (open)
7
WP
O
Write control signal output to the EEPROM (IC101)
8
TRM/XKRCS
—
Not used (open)
9
AVCC
—
Power supply terminal (+3.3V) (for A/D converter)
10
AVRH
—
Reference voltage input (+3.3V) terminal (for A/D converter)
11
AVSS
—
Ground terminal (for A/D converter)
12
AN0
I
Mode 0 set input terminal
13
AN1
I
Mode 1 set input terminal
14
AN2
I
Mode 2 set input terminal
15
AN3
I
Mode 3 set input terminal
16
INT0
I
Interrupt request signal input from the AV decoder (IC503)
17
INT1
I
Interrupt request signal input from the ARP (IC302)
18
INT2
I
Interrupt request signal input from the servo DSP (IC302)
19
INT3
I
Interrupt request signal input from the gate array (IC202)
20
INT4
I
Interrupt request signal input from the interface controller (IC401)
21, 22
INT5, INT6
—
Not used (fixed at “H”)
23
INT7
—
Not used (open)
24
VCC
—
Power supply terminal (+3.3V)
25
SI0
I
Serial data input from the interface controller (IC401)
26
SO0
O
Serial data output to the interface controller (IC401)
27
SC0
O
Serial clock signal output to the interface controller (IC401)
28
SI1
I
Serial data input terminal Not used (open)
29
SO1
O
Serial data output terminal Not used (open)
30
SC1
O
Serial clock signal output terminal Not used (open)
31
SI2
I
Serial data input terminal (for test)
32
SO2
O
Serial data output terminal (for test)
33
DSENS
—
Not used (open)
34
VSS
—
Ground terminal
35
XRST
O
System reset signal output terminal “L”: reset
36
XARPPST
O
Reset signal output to the ARP (IC302) “L”: reset
37
RGBSEL/MICMUTE
—
Not used (open)
38
SDA
I/O
Two-way data bus with EEPROM (IC101)
39
SCL
O
Serial clock signal output to the EEPROM (IC101)
40
TRM+/XKRRST
—
Not used (fixed at “L”)
41
EUROV/Y/CLAPSW1
—
Not used (open)
42
DISCEXT/CLPSW0
—
Not used (open)
43
MD0
I
Mode select 0 signal input terminal (fixed at “H” in this set)
44
MD1
I
Mode select 1 signal input terminal (fixed at “L” in this set)
45
MD2
I
Mode select 2 signal input terminal (fixed at “L” in this set)
46
DREQ0
I
Request 0 signal input from the AV decoder (IC503)
47
DACK0
O
Acknowledge 0 signal output to the AV decoder (IC503)
48
XDRVMUTE
O
Drive mute signal output terminal
49
DREQ1
I
Request 1 signal input from the AV decoder (IC503)
50
DACK1
O
Acknowledge 1 signal output to the AV decoder (IC503)
50
DVP-S9
Pin No.
Pin Name
I/O
Description
51
XIFCS
O
Chip select signal output to the interface controller (IC401)
52
VSS
—
Ground terminal
53
X1
O
System clock output terminal (16.5MHz)
54
X0
I
System clock input terminal (16.5MHz)
55
VCC
—
Power supply terminal (+3.3V)
56
CKSW1
—
Not used (open)
57
OCSSW1
—
Not used (open)
58
CS0X
O
Chip select signal output to the flash memory (IC107)
59
CS1X
—
Not used (open)
60
CS2X
O
Chip select signal output to the AV decoder (IC503)
61
CS3X
O
Chip select signal output to the AV decoder (IC503)
62
CS4X
O
Chip select signal output to the ARP (IC302)
63
CS5X
O
Chip select signal output to the Servo DSP (IC302)
64
C
—
Capacitor connected terminal
65
CS6X
O
Chip select signal output to the gate array (IC202)
66
CS7X
—
Not used (open)
67
XWAIT
I
Wait signal input terminal
68
BGRNTX
—
Not used (fixed at “H”)
69
BGR
—
Not used (open)
70
XRD
O
Read enable signal output terminal
71
XWRH
O
High byte write enable signal output terminal
72
XWRL
—
Not used (open)
73
NMIX
—
Not used (fixed at “H”)
74
HSTX
—
Not used (fixed at “H”)
75
VSS
—
Ground terminal
76
XFRRST
I
Reset signal input from the interface controller (IC401) “L”: reset
77
CPUCK
O
CPU clock signal output terminal
78
OCSW2
—
Not used (fixed at “H”)
79
XDACX
—
Not used (fixed at “H”)
80
VESCS/X39CS
—
Not used (fixed at “H”)
81
48/44.1K
O
Sampling frequency selection signal output terminal “L”: 48kHz, “H”: 44.1kHz
82
WIDE
O
Wide signal output terminal
83
MAMUTE
I
System OK signal input terminal
84
XLDON
O
LD control signal output terminal
85 to 100
HD0 to HD15
I/O
Two-way data bus terminal
101
VSS
—
Ground terminal
102 to 109
HA0 to HA7
O
Address signal output terminal
110
VCC
—
Power supply terminal (+3.3V)
111 to 118
HA8 to HA15
O
Address signal output terminal
119
VSS
—
Ground terminal
120
HA16
O
Address signal output terminal
51
DVP-S9
•
MB BOARD IC302 CXD9635R (SERVO DIGITAL SIGNAL PROCESSOR, ARP)
Pin No.
Pin Name
I/O
Description
1
VSS
—
Ground terminal (for digital system)
2 to 9
D0 to D7
I/O
Two-way data bus terminal
10
VDD 3.3V
—
Power supply terminal (+3.3V) (for digital system)
11 to 15
A0 to A4
I
Address signal input terminal
16
VSS
—
Ground terminal (for digital system)
17 to 19
A5 to A7
I
Address signal input terminal
20
VDD 1.8V
—
Power supply terminal (+1.8V) (for digital system)
21
XINT
O
Interrupt request signal output to the system controller (IC103)
22
HINT
O
Interrupt request signal output to the system controller (IC103)
23
XCS
I
Chip select signal input from the system controller (IC103)
24
HCS
I
Chip select signal input from the system controller (IC103)
25
XWAT
O
Wait signal output terminal
26
VSS
—
Ground terminal (for digital system)
27 to 36
MA0 to MA9
O
Address signal output to the D-RAM (IC303)
37
VDD 3.3V
—
Power supply terminal (+3.3V) (for digital system)
38
XMWR
O
Write enable signal output to the D-RAM (IC303)
39
XCAS
O
CAS signal output to the D-RAM (IC303)
40
VSS
—
Ground terminal (for digital system)
41
XRAS
O
RAS signal output to the D-RAM (IC303)
42
XOE
O
Output enable signal output to the D-RAM (IC303)
43
VDD1 1.8V
—
Power supply terminal (+1.8V) (for digital system)
44 to 51
MD0 to MD7
I/O
Two-way data bus with the D-RAM (IC303)
52
VSS
—
Ground terminal (for digital system)
53 to 60
MD8 to MD15
I/O
Two-way data bus with the D-RAM (IC303)
61
VDD 3.3V
—
Power supply terminal (+3.3V) (for digital system)
62
DATA
O
CD data output to the AV decoder (IC503)
63
BCLK
O
CD bit clock signal output to the AV decoder (IC503)
64
VSS
—
Ground terminal (for digital system)
65
LRCK
O
CD LR clock signal output to the AV decoder (IC503)
66
DOUT
O
Digital signal output to the AV decoder (IC503)
67
VDD 1.8V
—
Power supply terminal (+1.8V) (for digital system)
68
SDCK
O
SD bus clock signal output to the AV decoder (IC503)
69
XSHD
O
SD bus header signal output to the AV decoder (IC503)
70
XSRQ
I
SD bus request signal input from the AV decoder (IC503)
71
XSAK
O
SD bus acknowledge signal output to the AV decoder (IC503)
72
SDEF
O
SD bus error flag signal output to the AV decoder (IC503)
73 to 81
SD0 to SD7
O
SD bus data output to the AV decoder (IC503)
82
VDD 3.3V
—
Power supply terminal (+3.3V) (for digital system)
83 to 88
MNT0 to MNT5
I/O
Monitor signal input/output terminal Not used (open)
89, 90
MNT6, MNT7
I/O
Monitor signal input/output terminal Not used (fixed at “H”)
91
ESTB
O
Error strobe signal output terminal Not used (open)
92
VDD 1.8V
—
Power supply terminal (+1.8V) (for digital system)
93
RFD
I/O
RF digital data input/output terminal Not used (fixed at “H”)
94
VSS
—
Ground terminal (for digital system)
52
DVP-S9
Pin No.
Pin Name
I/O
Description
95
PLCKO
O
Not used (open)
96 to 103 ADO0 to ADO7
O
Not used (fixed at “H”)
104
VSS
—
Ground terminal (for digital system)
105
VSSA4
—
Ground terminal (for analog system)
106
VCO
I
VCO control signal input terminal
107, 108
R1, R2
I
VCO outside resistance signal input terminal
109
VDDA4 3.3V
—
Power supply terminal (+3.3V) (for analog system)
110
VSSA3
—
Ground terminal (for analog system)
111
INP
I
OP amp positive input terminal
112
INM
I
OP amp negative input terminal
113 to 115
FR3 to FR1
I
Feedback resistance signal input terminal
116
Y
O
OP amp output terminal
117
VDDA3 3.3V
—
Power supply terminal (+3.3V) (for analog system)
118
VREF
I
Reference voltage input terminal (for D/A converter)
119
BIAS
I
Bias input terminal (for D/A converter)
120
VDDA2 3.3V
—
Power supply terminal (+3.3V) (for analog system)
121
VSSA2
—
Ground terminal (for analog system)
122
AOUT
O
D/A converter output terminal (for D/A converter)
123
IREF
I
Reference current input terminal (for D/A converter)
124
VSSD2
—
Ground terminal (for D/A converter)
125
VDDD2 3.3V
—
Power supply terminal (+3.3V) (for D/A converter)
126
VRT
I
A/D converter reference input terminal
127
VDDA1 3.3V
—
Power supply terminal (+3.3V) (for analog system)
128
RFIN2
I
RF signal input terminal
129
NMIX
—
RF signal input terminal Not used
130
VSSA1
—
Ground terminal (for analog system)
131
RFIN1
I
RF signal input terminal
132
VRB
I
A/D converter reference input terminal
133
VSSD1
—
Ground terminal (for A/D converter)
134
VDDD1 3.3V
—
Power supply terminal (+3.3V) (for A/D converter)
135
ADC0
I
Tracking error signal input from the SP3728AC (IC001)
136
ADC1
I
Focusing error signal input from the SP3728AC (IC001)
137
ADC2
I
Pull-in signal input from the SP3728AC (IC001)
138
VDDA0 3.3V
—
Power supply terminal (+3.3V) (for analog system)
139
ADC3
I
Tracking coil drive signal input from the FAN8034 (IC401)
140
ADC4
I
Spindle motor drive signal input from the FAN8034 (IC401)
141
VSSA0
—
Ground terminal (for analog system)
142, 143
ADC5, ADC6
I
A/D converter input terminal
144
ADC7
I
Monitor signal input from the SP3728AC (IC001)
145
VDDD0 3.3V
—
Power supply terminal (+3.3V) (for A/D converter)
146
VSSD0
—
Ground terminal (for A/D converter)
147
VRBA
I
A/D converter reference input terminal
148
VSSA0
—
Ground terminal (for analog system)
149
TESTAA
O
ASW output terminal Not used (open)
150
VDDA0 3.3V
—
Power supply terminal (+3.3V) (for analog system)
Click on the first or last page to see other DVP-S9 / MHC-S9D service manuals if exist.