Sony DHC-FLX9W / HCD-FLX9W Service Manual ▷ View online
113
HCD-FLX9W
MB BOARD IC901 CXP973064-236R (MECHANISM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
EEP SO
O
Not used
2
SDEN
O
Serial data enable signal output to DVD/CD RF amplifier
3
DOCTRL/
ISBTEST
O
Digital out on/off control signal output to the digital signal processor
“L”: digital out off, “H”: digital out on
“L”: digital out off, “H”: digital out on
4
EEP WC
O
Not used
5
EEP SI
I/O
Two-way data bus with the EEPROM
6
EEP RDY
I
EEPROM ready signal input from the DVD decoder
7
FCS JMP 1
O
Focus jump 1 signal output to the motor/coil driver
8
FCS JMP 2
O
Focus jump 2 signal output to the motor/coil driver
9
SENS CD
I
Internal status (SENSE) signal input from the digital signal processor
10
LOAD +
O
Loading motor drive signal (loading in direction) output terminal Not used
11
LOAD –
O
Loading motor drive signal (loading out direction) output terminal Not used
12
XCS DVD
O
Chip select signal output to the DVD decoder
13
VSS
—
Ground terminal (digital system)
14 to 21
D0 to D7
I/O
Two-way data bus with the DVD decoder
22
INIT0 DVD
I
Interrupt signal input from the DVD decoder
23
INIT1 DVD
I
Interrupt signal input from the DVD decoder
24
SCK DSD
O
Serial data transfer clock signal output to the DSD decoder
25
XRST DVD
O
Reset signal output to the DVD decoder “L”: reset
26
SCOR
I
Subcode sync (S0+S1) detection signal input from the digital signal processor
27
LAT CD
O
Serial data latch pulse signal output to the digital signal processor
28
LD ON
O
Laser diode on/off control signal output to the DVD/CD RF amplifier
“L”: laser diode off, “H”: laser diode on
“L”: laser diode off, “H”: laser diode on
29
MIRR
I
Mirror signal input from the digital signal processor
30
COUT CD
I
Numbers of track counted signal input from the digital signal processor
31
INLIM
I
Detection signal input from limit in switch The optical pick-up is inner position when “H”
32
CS ZIVA
O
Chip select signal output to the DVD system processor
33
SI ZIVA
I
Serial data input from the DVD system processor
34
SO ZIVA
O
Serial data output to the DVD system processor
35
SCK ZIVA
O
Serial data transfer clock signal output to the DVD system processor
36
DRVIRQ
O
Interrupt request signal output to the DVD system processor
37
DRVRDY
O
Ready signal output to the DVD system processor
38
RST
I
System reset signal input from the DVD system processor “L”: reset
39
VSS
—
Ground terminal (digital system)
40
XTAL O
System clock output terminal (20 MHz)
41
EXTAL I
System clock input terminal (20 MHz)
42
VDD
—
Power supply terminal (+3.3V) (digital system)
43, 44
SLED A, SLED B
O
Sled motor drive signal output
45
JIT OFFSET
O
Output terminal for offset adjustment of APEO (<z/. pin of DVD decoder)
46
SDOUT DSD
O
Serial data output to the DSD decoder
47
SDIN DSD
I
Serial data input from the DSD decoder
48
READY DSD
I
Ready signal input from the DSD decoder “L”: ready
49
DATA CD
O
Serial data output to the digital signal processor
50
CLOK CD
O
Serial data transfer clock signal output to the digital signal processor
51
XMSLAT
O
Serial data latch pulse signal output to the DSD decoder
114
HCD-FLX9W
Pin No.
Pin Name
I/O
Description
52
SQSO
I
Subcode Q data input from the digital signal processor
53
MUTE DSD
O
Muting on/off control signal output to the DSD decoder “H”: muting on
54
SQCK
O
Subcode Q data reading clock signal output to the digital signal processor
55
VSS
—
Ground terminal (digital system)
56
TRAY IN
I
Disc tray in detection signal input terminal Not used
57
TRAY OUT
I
Disc tray out detection signal input terminal Not used
58
GFS DVD
I
Guard frame sync signal input from the DVD decoder
59
MUTE CD
O
Muting on/off control signal output to the digital signal processor “H”: muting on
60
MUTE 2D
O
Muting on/off control signal output to the motor/coil driver “H”: muting on
61
SLED
I
Sled motor servo drive PWM signal input terminal
62
FG
I
Spindle motor control signal input
63
SP ON
O
Muting on/off control signal output to the motor/coil driver “H”: muting on
64
JIT
I
Jitter signal input
65
TE
I
Tracking error signal input from the DVD/CD RF amplifier
66
PI
I
Pull in signal input from the DVD/CD RF amplifier
67
FE
I
Focus error signal input from the DVD/CD RF amplifier
68
AVSS
—
Ground terminal (for A/D converter)
69
AVREF
I
Reference voltage input terminal (for A/D converter)
70
AVDD
—
Power supply terminal (+3.3V) (for A/D converter)
71
GFS CD
I
Guard frame sync signal input from the digital signal processor
72
SCLK CD
O
SENSE serial data reading clock signal output to the digital signal processor
73
TSD
O
Thermal shut down signal output to the motor/coil driver
74
FOK CD
I
Focus OK signal input from the digital signal processor
75
LOCK CD
I
GFS is sampled by 460 Hz “H” input when GFS is “H”
76
LDSEL
O
Laser diode selection signal output
77
SACD/DVD
O
SACD/DVD selection signal output “L”: DVD, “H”: SACD
78
I2C SIO
I/O
Communication data bus with the DVD system processor and system controller
79
I2C SCL
I/O
Communication data reading clock signal input or transfer clock signal output with the DVD
system processor and system controller
system processor and system controller
80
RXD
I
Serial data input from the RS-232C (for check)
81
TXD
O
Serial data output to the RS-232C (for check)
82
SDCLK RF
O
Serial data transfer clock signal output to the DVD/CD RF amplifier
83
SDATA RF
I/O
Two-way data bus with the DVD/CD RF amplifier
84
XWR
O
Write strobe signal output to the DVD decoder
85
XRD
O
Read strobe signal output to the DVD decoder
86
(PWE)
—
Not used
87
VDD
—
Power supply terminal (+3.3V) (digital system)
88
VSS
—
Ground terminal (digital system)
89 to 96
A0 to A7
O
Address signal output to the DVD decoder
97
DSAVE
O
Motor/coil driver power save control signal output terminal Not used
98
XDRST
O
Reset signal output to the digital signal processor and DSD decoder “L”: reset
99
EEP WP
O
Write protect signal output to the EEPROM
100
EEP CLK
O
Clock signal output to the EEPROM
115
HCD-FLX9W
DSP BOARD IC601 CXD9720Q (AUDIO DIGITAL SIGNAL PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
VSS
—
Ground terminal
2
XRST
I
Reset signal input from the digital audio interface receiver “L”: reset
3
EXTIN
I
Master clock signal input terminal Not used
4
LRCKI3
I
L/R sampling clock signal input from the A/D converter or digital audio interface receiver or
digital audio processor
digital audio processor
5
VDDI
—
Power supply terminal (+3.3V)
6
BCKI3
I
Bit clock signal (2.8224 MHz) input from the A/D converter or digital audio interface receiver or
digital audio processor
digital audio processor
7
PLOCK
O
Internal PLL lock signal output terminal Not used
8
VSS
—
Ground terminal
9
MCLK1
I
System clock input terminal (13 MHz)
10
VDDI
—
Power supply terminal (+3.3V)
11
VSS
—
Ground terminal
12
MCLK2
O
System clock output terminal (13 MHz)
13
MS
I
Master/slave selection signal input terminal “L”: slave, “H”: master (fixed at “L” in this set)
14
SCKOUT
O
Internal system clock signal output to the D/A converter
15
LRCKI1
I
L/R sampling clock signal input from the A/D converter or digital audio interface receiver or
digital audio processor
digital audio processor
16
VDDE
—
Power supply terminal (+3.3V)
17
BCKI1
I
Bit clock signal (2.8224 MHz) input from the A/D converter or digital audio interface receiver or
digital audio processor
digital audio processor
18
SDI1
I
Audio serial data input from the digital audio interface receiver or digital audio processor
19
LRCKO
O
L/R sampling clock signal (44.1 kHz) output to the D/A converter and RF modulator
20
BCKO
O
Bit clock signal (2.8224 MHz) output to the D/A converter and RF modulator
21
VSS
—
Ground terminal
22
KFSIO
I
Audio clock signal input from the A/D converter or digital audio interface receiver
23
SDO1
O
Audio serial data output to the D/A converter
24
SDO2
O
Audio serial data output to the D/A converter and RF modulator
25
SDO3
O
Audio serial data output to the D/A converter
26
SDO4
O
Audio serial data output to the D/A converter
27
SPDIF
O
S/PDIF signal output terminal Not used
28
LRCKI2
I
L/R sampling clock signal input from the A/D converter or digital audio interface receiver or
digital audio processor
digital audio processor
29
BCKI2
I
Bit clock signal (2.8224 MHz) input from the A/D converter or digital audio interface receiver or
digital audio processor
digital audio processor
30
SDI2
I
Audio serial data input from the A/D converter
31
VSS
—
Ground terminal
32
HACN
O
Acknowledge signal output to the system controller
33
HDIN
I
Write data input from the system controller
34
HCLK
I
Clock signal input from the system controller
35
HDOUT
O
Read data output to the system controller
36
HCS
I
Chip select signal input from the system controller
37
GP12
O
Clock signal output terminal Not used
38
GP13
O
Clock enable signal output terminal Not used
39
GP14
O
Row address strobe signal output terminal Not used
116
HCD-FLX9W
Pin No.
Pin Name
I/O
Description
40
VDDI
—
Power supply terminal (+3.3V)
41
VSS
—
Ground terminal
42
GP15
O
Column address strobe signal output terminal Not used
43
OE0
O
Output enable signal output to the S-RAM
44
CS0
O
Chip select signal output to the S-RAM
45
WE0
O
Write enable signal output to the S-RAM
46
VDDE
—
Power supply terminal (+3.3V)
47
WMD1
I
S-RAM wait mode setting terminal Fixed at “H” in this set
48
VSS
—
Ground terminal
49
WMD0
I
S-RAM wait mode setting terminal Fixed at “L” in this set
50
PAGE2
O
Page selection signal output terminal Not used
51
VSS
—
Ground terminal
52, 53
PAGE1, PAGE0
O
Page selection signal output terminal Not used
54
BOOT
I
Boot mode control signal input terminal Not used
55
BTACT
O
Boot mode state display signal output terminal Not used
56
BST
I
Boot trap signal input from the digital audio interface receiver
57
MOD1
I
PLL input frequency select terminal “L”: 384fs, “H”: 256fs (fixed at “H” in this set)
58
MOD0
I
Mode setting terminal “L”: single chip mode, “H”: use prohibition (fixed at “L” in this set)
59
EXLOCK
I
PLL lock error and data error flag input from the digital audio interface receiver
60
VDDI
—
Power supply terminal (+3.3V)
61
VSS
—
Ground terminal
62, 63
A17, A16
O
Address signal output terminal Not used
64 to 66
A15 to A13
O
Address signal output to the S-RAM
67
GP10
O
L/R sampling clock signal (44.1 kHz) output to the D/A, A/D converter and digital filter
Not used
Not used
68
DECODE
O
Decode signal output to the system controller
69
AUDIO
I
Bit 1 input terminal of channel status from the digital audio interface receiver
70
VDDI
—
Power supply terminal (+3.3V)
71
VSS
—
Ground terminal
72 to 75
D15 to D12
I/O
Two-way data bus with the S-RAM
76
VDDE
—
Power supply terminal (+3.3V)
77 to 80
D11 to D8
I/O
Two-way data bus with the S-RAM
81
VSS
—
Ground terminal
82 to 85
A9, A12 to A10
O
Address signal output to the S-RAM
86
TDO
O
Simple emulation data output terminal Not used
87
TMS
I
Simple emulation data input start/end detection signal input terminal Not used
88
XTRST
I
Simple emulation asychronous break input terminal Not used
89
TCK
I
Simple emulation clock signal input terminal Not used
90
TDI
I
Simple emulation data input terminal Not used
91
VSS
—
Ground terminal
92 to 97
A8 to A3
O
Address signal output to the S-RAM
98, 99
D7, D6
I/O
Two-way data bus with the S-RAM
100
VDDI
—
Power supply terminal (+3.3V)
101
VSS
—
Ground terminal
102 to 105
D5 to D2
I/O
Two-way data bus with the S-RAM
106
VDDE
—
Power supply terminal (+3.3V)
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