Sony DHC-FLX9W / HCD-FLX9W Service Manual ▷ View online
101
HCD-FLX9W
Pin No.
Pin Name
I/O
Description
86
MDQM2
O
Write mask signal output to the SD-RAM
87
VDD25
—
Power supply terminal (+3.3V)
88 to 95
MD20 to MD27
I/O
Two-way data bus with the SD-RAM
96
GND25
—
Ground terminal
97
MDQM3
O
Write mask signal output to the SD-RAM
98
VDD25
—
Power supply terminal (+3.3V)
99 to 102 MD28 to MD31
I/O
Two-way data bus with the SD-RAM
103
GND25
—
Ground terminal
104
VDD25
—
Power supply terminal (+3.3V)
105
VCLK
O
Not used
106
I2C_CTRL
O
Not used
107
VS
O
Wide control signal output terminal
108
I/P SW
O
Interlace/progressive selection signal output terminal Not used
109
GPIO1 (5)
O
Not used
110
GPIO1 (4)
O
Not used
111
VDDP
—
Power supply terminal (+3.3V)
112
GNDP
—
Ground terminal
113
GPIO1 (3)
O
Not used
114
GPIO1 (2)
O
Not used
115
GPIO1 (1)
O
Not used
116
HIRQ2
I
Busy signal input from the EEPROM
117
VDAC_4B
—
Ground terminal
118
VDAC_VDD4
—
Power supply terminal (+3.3V)
119
VDAC_4
O
Component video signal output to the video amplifier
120
VDAC_3B
—
Ground terminal
121
VDAC_VDD3
—
Power supply terminal (+3.3V)
122
VDAC_3
O
Component video signal output to the video amplifier
123
VDAC_2B
—
Ground terminal
124
VDAC_VDD2
—
Power supply terminal (+3.3V)
125
VDAC_2
O
Y (luminance) video signal output to the video amplifier
126
VDAC_1B
—
Ground terminal
127
VDAC_VDD1
—
Power supply terminal (+3.3V)
128
VDAC_1
O
C (chroma) video signal output to the video amplifier
129
VDAC_0B
—
Ground terminal
130
VDAC_VDD0
—
Power supply terminal (+3.3V)
131
VDAC_0
O
Video signal output to the video amplifier
132
VDAC_DVSS
—
Ground terminal
133
VDAC_DVDD
—
Power supply terminal (+3.3V)
134
VDAC_REFVDD
—
Power supply terminal
135
VDAC_REF
I
Power supply terminal (+3.3V)
136
VDAC_REFVSS
—
Ground terminal
137
XVSS
—
Ground terminal
138
XOUT
O
Clock signal output terminal Not used
139
XIN
I
System clock signal (33.8688 MHz) input from the clock generator
140
XVDD
—
Power supply terminal
141
AVSS2
—
Ground terminal
102
HCD-FLX9W
Pin No.
Pin Name
I/O
Description
142
AVDD2
—
Power supply terminal (+3.3V)
143
AVDD1
—
Power supply terminal (+3.3V)
144
AVSS1
—
Ground terminal
145
VDD
—
Power supply terminal (+1.8V)
146
GND
—
Ground terminal
147
XCK
O
Audio system clock output terminal Not used
148
LRCK
O
L/R sampling clock signal (44.1 kHz) output terminal Not used
149
BCK
O
Bit clock signal (2.8224 MHz) l output terminal Not used
150
GPIO4 (1)
O
Not used
151
GPIO4 (2)
O
Not used
152
VDDP
—
Power supply terminal (+3.3V)
153
GNDP
—
Ground terminal
154
GPIO4 (3)
O
Not used
155
GPIO4 (4)
O
Not used
156
IEC958
O
SPDIF signal output terminal
157
CS_EEPROM
O
Chip select signal output to the EEPROM
158
WC_EEPROM
O
Write control signal output to the EEPROM
159
CS_SPC
O
Not used
160
I2C_CL
I/O
Two-way I2C clock bus with the mechanism controller and system controller
161
I2C_DA
I/O
Two-way I2C data bus with the mechanism controller and system controller
162
RTSI
I
Not used
163
RXD1
I
Serial data input terminal Not used
164
TXD1
O
Serial data output terminal Not used
165
CTSI
I
Not used
166
GNDP
—
Ground terminal
167
VDDP
—
Power supply terminal (+3.3V)
168 to 171
SDDATA7 to
SDDATA4
I
Stream data signal input from the DVD decoder
172
GND
—
Ground terminal
173
VDD
—
Power supply terminal (+1.8V)
174 to 177
SDDATA3 to
SDDATA0
I
Stream data signal input from the DVD decoder
178
SDREQ
O
Serial data request signal output to the DVD decoder
179
SDEN
I
Serial data enable signal input from the DVD decoder
180
GNDP
—
Ground terminal
181
VDDP
—
Power supply terminal (+3.3V)
182
SDERROR
I
Serial data error signal input from the DVD decoder
183
SDCLK
I
Serial data clock signal input from the DVD decoder
184
HIRQ1
I
Interrupt request signal input from the mechanism controller
185
DRVCLK
I
Serial data transfer clock signal input from the mechanism controller
186
DRVTX
I
Serial data input from the EEPROM and mechanism controller
187
DRVRX
O
Serial data output to the EEPROM and mechanism controller
188
DRVRDY
I
Ready signal input from the mechanism controller
189
VNW
—
Power supply terminal (+5V)
190
ALE
O
Latch enable signal output to the bus interface
191
RST_SPC
O
Reset signal output to the mechanism controller
103
HCD-FLX9W
Pin No.
Pin Name
I/O
Description
192 to 194
HCS3 to HCS1
O
Chip select signal output terminal Not used
195
HCS0
O
Chip select signal output to the program ROM
196
VDDP
—
Power supply terminal (+3.3V)
197
TRST
O
Reset signal output to the DSD decoder
198
TDO
O
Data output to the DSD decoder
199
TDI
I
Data input terminal Not used
200
TMS
O
Mode selection signal output to the DSD decoder
201
TCK
O
Clock signal output to the DSD decoder
202
RESET
I
Reset signal input from the system controller “L”: reset
203
BUS CLK
O
Not used
204
GND
—
Ground terminal
205
VDD
—
Power supply terminal (+1.8V)
206, 207
HA3, HA2
O
Address signal output to the program ROM and bus interface
208
GNDP
—
Ground terminal
104
HCD-FLX9W
MB BOARD IC509 CXD3068Q (DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
DVDD0
—
Power supply terminal (+3.3V) (digital system)
2
XRST
I
Reset signal input from the mechanism controller “L”: reset
3
MUTE
I
Muting on/off control signal input from the mechanism controller “H”: muting on
4
DATA
I
Serial data input from the mechanism controller
5
XLAT
I
Serial data latch pulse signal input from the mechanism controller
6
CLOK
I
Serial data transfer clock signal input from the mechanism controller
7
SENS
O
Internal status (SENSE) signal output to the mechanism controller
8
SCLK
I
SENSE serial data reading clock signal input from the mechanism controller
9
ATSK
I/O
Input/output terminal for anti-shock Not used
10
WFCK
O
Write frame clock signal output to the DVD decoder
11
RFCK
O
RFCK signal output terminal Not used
12
XPCK
O
XPCK signal output terminal Not used
13
GFS
O
Guard frame sync signal output to the mechanism controller
14
C2PO
O
C2 pointer signal output to the DVD decoder
15
SCOR
O
Subcode sync (S0+S1) detection signal output to the DVD decoder and mechanism controller
16
C4M
O
4.2336 MHz clock signal output terminal Not used
17
WDCK
O
Guard subcode sync (S0+S1) detection signal output to the DVD decoder
18
DVSS0
—
Ground terminal (digital system)
19
COUT
O
Numbers of track counted signal output to the mechanism controller
20
MIRR
O
Mirror signal output to the mechanism controller
21
DFCT
I/O
Defect signal input/output terminal Not used
22
FOK
O
Focus OK signal output to the mechanism controller
23
PWMI
I
Spindle motor external control signal input terminal Not used
24
LOCK
O
GFS is sampled by 460 Hz “H” output when GFS is “H”
25
MDP
O
Spindle motor servo drive signal output to the DVD decoder
26
SSTP
I
Detection signal input from limit in switch The optical pick-up is inner position when “H”
27
FSTO
O
2/3 divider output terminal Not used
28
DVDD1
—
Power supply terminal (+3.3V) (digital system)
29
SFDR
O
Sled servo drive PWM signal (+) output
30
SRDR
O
Sled servo drive PWM signal (–) output
31
TFDR
O
Tracking servo drive PWM signal (+) output
32
TRDR
O
Tracking servo drive PWM signal (–) output
33
FFDR
O
Focus servo drive PWM signal (+) output
34
FRDR
O
Focus servo drive PWM signal (–) output
35
DVSS1
—
Ground terminal (digital system)
36
TEST
I
Input terminal for the test
37
TES1
I
Input terminal for the test
38
VC
I
Middle point voltage (+1.65V) input terminal
39
FE
I
Focus error signal input from the DVD/CD RF amplifier
40
SE
I
Sled error signal input from the DVD/CD RF amplifier
41
TE
I
Tracking error signal input from the DVD/CD RF amplifier
42
CE
I
Middle point servo analog signal input
43
RFDC
I
RF signal input from the DVD/CD RF amplifier
44
ADIO
O
Output terminal for the test Not used
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