Sony DHC-EX77MD / DHC-MD77 / MDS-EX77 / MDS-EX770 Service Manual ▷ View online
– 57 –
– MAIN/DISPLAY Section –
IC101
CXA8065S
–
+
1
2
3
4
5
6
7
8
9
31
30
29
28
27
26
25
24
23
13.2k
2.35k
2.35k
13.2k
13.2k
V
CC
10
11
12
13
22
21
20
19
36
35
34
33
32
16
17
18
14
15
–
+
–
+
–
+
–
+
+
–
–
+
–
+
+
–
+
–
V
EE
LINE02
PMUTE
LINE01
MUTE
LINE/MIC
+D/A1
+D/A1
+D/AO1
LP1N1
LPOUT1
GND1
LPOUT2
LPIN2
D/AO2
–D/A2
+D/A2
V
CC
V
DD
–
+
LINE1
V
EE
MIC1
SW01
SWI1
–A/D1
INV1
+A/D1
A/DREF
VREF
+A/D2
INV2
–A/D2
SWI2
SWO2
MIC2
GND2
LINE2
IC201
CXD8607N
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
INRP
INRM
REFI
AVDD
AVSS
APD
NU
NU
TEST1
LRCK1
BCK1
ADDT
V35A
VSS1 (LF)
MCKI
DPD
VSS2(LF)
INIT
MODE
SHIFT
LATCH
256CK
V35D
VSS2
512CK
BCK2
DADT
LRCK2
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
INLP
INLM
REFO
LVSS
LVDD
AVSS(LF)
NU
NU
VSS1(LF)
TEST3
TEST2
VSS1
VDD1
VDD1
VDD2
L1
AVDDL
L2
AVSSL
XVSS
XIN
XOUT
XVDD
AVSSR
R2
AVDDR
R1
VDD2
MODULATOR
MODULATOR
DECIMATION
FILTER
DECIMATION
FILTER
LOW CUT
FILTER
LOW CUT
FILTER
VOLTAGE
REFERENCE
I/O
I/O
ATT
PLM
OVER
SAMP
FILTER
MOIZE
SHAPER
CPU
INTERFACE
+
–
+
–
ATT
PLM
OVER
SAMP
FILTER
NOIZE
SHAPER
– 58 –
IC311
LB1641
1
2
3
4
5
6
7
8
9
10
GND
MOTOR
DRIVE
NOISE
FILTER
CLAMP
FWD.IN
REV.IN
VCC 1
VCC 2
NOISE
FILTER
MOTOR
DRIVE
MOTOR
DRIVE
MOTOR
DRIVE
T.S.D
O.C.P
FWD/REV/STOP
CONTROL LOGIC
1
–
+
12
DELAY
CIRCUIT
VREF
DELAY
CIRCUIT
3.3V
PH5
STBY
V
CC
ANA5
SYS3.3
BACK
AC
CD1
P. DOWN
GND
CD2
S. RESET
–
+
–
+
–
+
–
+
–
+
2
3
4
5
6
7
8
9
10
11
IC501
LA5620
– 59 –
6-7.
IC PIN FUNCTION DESCRIPTION
BD BOARD IC101 CXA2523R (RF AMPLIFIER)
Pin No. Pin Name
I / O
Function
1
I
I
I-V converted RF signal I input from the optical pick-up block detector
2
J
I
I-V converted RF signal J input from the optical pick-up block detector
3
VC
O
Middle point voltage (+1.65V) generation output terminal
4 to 9
A to F
I
Signal input from the optical pick-up detector
10
PD
I
Light amount monitor input terminal
11
APC
O
Laser amplifier output terminal to the automatic power control circuit
12
APCREF
I
Reference voltage input terminal for setting laser power
13
GND
—
Ground terminal
14
TEMPI
I
Connected to the temperature sensor
15
TEMPR
O
Output terminal for a temperature sensor reference voltage
16
SWDT
I
Writing serial data input from the CXD2650R (IC121)
17
SCLK
I
Serial clock signal input from the CXD2650R (IC121)
18
XLAT
I
Serial latch signal input from the CXD2650R (IC121)
19
XSTBY
I
Standby signal input terminal “L”: standby (fixed at “H” in this set)
20
F0CNT
I
Center frequency control voltage input terminal of internal circuit (BPF22, BPF3T, EQ) input from
the CXD2650R (IC121)
the CXD2650R (IC121)
21
VREF
O
Reference voltage output terminal Not used (open)
22
EQADJ
I
Center frequency setting terminal for the internal circuit (EQ)
23
3TADJ
I
Center frequency setting terminal for the internal circuit (BPF3T)
24
VCC
—
Power supply terminal (+3.3V)
25
WBLADJ
I
Center frequency setting terminal for the internal circuit (BPF22)
26
TE
O
Tracking error signal output to the CXD2650R (IC121)
27
CSLED
I
Connected to the external capacitor for low-pass filter of the sled error signal
28
SE
O
Sled error signal output to the CXD2650R (IC121)
29
ADFM
O
FM signal output of the ADIP
30
ADIN
I
Receives a ADIP FM signal in AC coupling
31
ADAGC
I
Connected to the external capacitor for ADIP AGC
32
ADFG
O
ADIP duplex signal (22.05 kHz
±
1 kHz) output to the CXD2650R (IC121)
33
AUX
O
Auxiliary signal (I
3
signal/temperature signal) output to the CXD2650R (IC121)
34
FE
O
Focus error signal output to the CXD2650R (IC121)
35
ABCD
O
Light amount signal (ABCD) output to the CXD2650R (IC121)
36
BOTM
O
Light amount signal (RF/ABCD) bottom hold output to the CXD2650R (IC121)
37
PEAK
O
Light amount signal (RF/ABCD) peak hold output to the CXD2650R (IC121)
38
RF
O
Playback EFM RF signal output to the CXD2650R (IC121)
39
RFAGC
I
Connected to the external capacitor for RF auto gain control circuit
40
AGCI
I
Receives a RF signal in AC coupling
41
COMPO
O
User comparator output terminal Not used (open)
42
COMPP
I
User comparator input terminal Not used (fixed at “L”)
43
ADDC
I
Connected to the external capacitor for cutting the low band of the ADIP amplifier
44
OPO
O
User operational amplifier output terminal Not used (open)
45
OPN
I
User operational amplifier inversion input terminal Not used (fixed at “L”)
46
RFO
O
RF signal output terminal
47
MORFI
I
Receives a MO RF signal in AC coupling
48
MORFO
O
MO RF signal output terminal
– 60 –
Pin No. Pin Name
I / O
Function
1
FOK
O
Focus OK signal output to the system controller (IC401) “H” is output when focus is on
2
SHCK
O
Track jump detection signal output to the system controller (IC401)
3
XBUSY
O
Monitor 2 signal output to the system controller (IC401)
4
SLOC
O
Monitor 3 signal output to the system controller (IC401)
5
SWDT
I
Writing data signal input from the system controller (IC401)
6
SCLK
I
Serial clock signal input from the system controller (IC401)
7
XLAT
I
Serial latch signal input from the system controller (IC401)
8
SRDT
O (3)
Reading data signal output to the system controller (IC401)
9
SENS
O (3)
Internal status (SENSE) output to the system controller (IC401)
10
XRST
I
Reset signal input from the system controller (IC401) “L”: reset
11
SQSY
O
Subcode Q sync (SCOR) output to the system controller (IC401)
“L” is output every 13.3 msec Almost all, “H” is output
“L” is output every 13.3 msec Almost all, “H” is output
12
DQSY
O
Digital In U-bit CD format subcode Q sync (SCOR) output to the system controller (IC401)
“L” is output every 13.3 msec Almost all, “H” is output
“L” is output every 13.3 msec Almost all, “H” is output
13
RECP
I
Laser power selection signal input from the system controller (IC401)
“H”: recording mode, “L”: playback mode
“H”: recording mode, “L”: playback mode
14
XINT
O
Interrupt status output to the system controller (IC401)
15
TX
I
Recording data output enable signal input from the system controller (IC401)
Writing data transmission timing input (Also serves as the magnetic head on/off output)
Writing data transmission timing input (Also serves as the magnetic head on/off output)
16
OSCI
I
System clock signal (512Fs=22.5792 MHz) input from the A/D, D/A converter (IC201)
17
OSCO
O
System clock signal (512Fs=22.5792 MHz) output terminal Not used (open)
18
XTSL
I
Input terminal for the system clock frequency setting
“L”: 45.1584 MHz, “H”: 22.5792 MHz (fixed at “H” in this set)
“L”: 45.1584 MHz, “H”: 22.5792 MHz (fixed at “H” in this set)
19
RVDD
—
Power supply terminal (+3.3V) (digital system)
20
RVSS
—
Ground terminal (digital system)
21
DIN
I
Digital audio signal input terminal when recording mode (for optical in)
22
DOUT
O
Digital audio signal output terminal when playback mode (for optical out) Not used
23
ADDT
I
Recording data input from the A/D, D/A converter (IC201)
24
DADT
O
Playback data output to the A/D, D/A converter (IC201)
25
LRCK
O
L/R sampling clock signal (44.1 kHz) output to the A/D, D/A converter (IC201)
26
XBCK
O
Bit clock signal (2.8224 MHz) output to the A/D, D/A converter (IC201)
27
FS256
O
Clock signal (11.2896 MHz) output terminal Not used (open)
28
DVDD
—
Power supply terminal (+3.3V) (digital system)
29
A03
O
30
A02
O
31
A01
O
32
A00
O
33
A10
O
34
A04
O
Address signal output to the external D-RAM Not used (open)
35
A05
O
36
A06
O
37
A07
O
38
A08
O
39
A11
O
BD BOARD IC121 CXD2650R
(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR, EFM/ACIRC ENCODER/DECODER,
SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER, 2M BIT D-RAM)
(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR, EFM/ACIRC ENCODER/DECODER,
SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER, 2M BIT D-RAM)
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