Sony DAV-X1 / HCD-X1 Service Manual ▷ View online
81
HCD-X1
MIB01 BOARD IC506 ADV7300AKST (VIDEO ENCODER)
Pin No.
Pin Name
I/O
Description
1
VDD_IO
-
Power supply terminal (+3.3V)
2 to 9
P_Y (0) to P_Y (7)
I
Video signal input from the progressive scan converter
10
VDD
-
Power supply terminal (+2.5V)
11
GND
-
Ground terminal
12, 13
P_Y (8), P_Y (9)
I
Video signal input from the progressive scan converter
14 to 18
P_C (0) to P_C (4)
I
Video signal input from the progressive scan converter
19
SPI_II2_EN
-
Not used
20
ALS8
-
Not used
21
SDA
I/O
Two-way data bus with the servo DSP
22
SCL
I
Serial data transfer clock signal input from the servo DSP
23
P_HSYNC
I
Horizontal sync signal input terminal Not used
24
P_VSYNC
I
Vertical sync signal input terminal Not used
25
P_BLANK
I
Blanking signal input terminal Not used
26 to 30
P_C (5) to P_C (9)
I
Video signal input from the progressive scan converter
31
RTC/SCRESET/TR
-
Not used
32
CLKIN
I
System clock input (27 MHz) from the progressive scan converter
33
RESET
I
System reset signal input from the servo DSP "L": reset
34
EXT_LF
I
Connected to the external loop filter
35
RSET2
I
Component video signal output level adjustment signal terminal
36
COMP2
-
Not used
37
CR/B
O
Video signal (red) output to the video amplifier
38
CB/R
O
Video signal (blue) output to the video amplifier
39
Y/G
O
Video signal (green) output to the video amplifier
40
GND
-
Ground terminal
41
VAA
-
Power supply terminal (+2.5V)
42
C
O
Chroma video signal output to the video amplifier
43
Y
O
Luma video signal output to the video amplifier
44
V
O
CVBS video signal output to the video amplifier
45
COMP1
-
Not used
46
VREF
-
Not used
47
RSET1
I
Composite video signal output level adjustment signal terminal
48
S_BLANK
I
Blanking signal input terminal Not used
49
S_VSYNC
I
Vertical sync signal input terminal Not used
50
S_HSYNC
I
Horizontal sync signal input terminal Not used
51, 52
S (0), S (1)
I
Video signal input terminal Not used
53 to 55
S (2) to S (4)
I
Video signal input from the progressive scan converter
56
VDD
-
Power supply terminal (+2.5V)
57
GND
-
Ground terminal
58 to 62
S (5) to S (9)
I
Video signal input from the progressive scan converter
63
CLKIN_2
I
System clock input (27 MHz) from the progressive scan converter
64
GND_IO
-
Ground terminal
82
HCD-X1
MIB01 BOARD IC507 CXD9836R (PIXEL RESOLUTION CONVERTER)
Pin No.
Pin Name
I/O
Description
1
VSS
-
Ground terminal
2
XTCK1
I
Terminal for test Fixed at "L" in this set
3
XSM
I
Terminal for test Fixed at "H" in this set
4
XTST
I
Terminal for test Fixed at "H" in this set
5
MST
I
Terminal for test Fixed at "L" in this set
6
SMCK
I
Terminal for test Fixed at "H" in this set
7 to 9
DC9 to DC7
I
Video signal input from the progressive scan converter
10
VDDI
-
Power supply terminal (+2.5V) (for core)
11
VSS
-
Ground terminal
12 to 15
DC6 to DC3
I
Video signal input from the progressive scan converter
16
VDDE
-
Power supply terminal (+3.3V) (for I/O)
17 to 19
DC2 to DC0
I
Video signal input from the progressive scan converter
20
DY0
I
Video signal input from the progressive scan converter
21
VSS
-
Ground terminal
22 to 30
DY1 to DY9
I
Video signal input from the progressive scan converter
31
VSS
-
Ground terminal
32 to 39
DI0 to DI7
I
Video signal input from the progressive scan converter
40
VDDI
-
Power supply terminal (+2.5V) (for core)
41
VSS
-
Ground terminal
42, 43
DI8, DI9
I
Video signal input from the progressive scan converter
44
DH
I
Horizontal sync signal input terminal Not used
45
DV
I
Vertical sync signal input terminal Not used
46
VDDE
-
Power supply terminal (+3.3V) (for I/O)
47
F1
I
Field flag control signal input terminal Not used
48
ALSB
I
IIC slave address setting terminal
Slave address setting: 0 x 28 when ALSB is "0", 0 x 2A when ALSB is "1"
Slave address setting: 0 x 28 when ALSB is "0", 0 x 2A when ALSB is "1"
49
SDA
I/O
Two-way data bus with the HDMI controller
50
SCL
I
Serial data transfer clock signal input from the HDMI controller
51
VSS
-
Ground terminal
52
NRST
I
System reset signal input from the HDMI controller "L": reset
53
TEST0
I
Terminal for test Fixed at "L" in this set
54
TEST1
I
Terminal for test Fixed at "L" in this set
55
TEST2
I
Terminal for test Fixed at "L" in this set
56
TEST3
I
Terminal for test Fixed at "L" in this set
57, 58
QB0, QB1
O
Video signal (blue) output terminal Not used
59
OVDDE1
-
Power supply terminal (+3.3V) (for I/O)
60
VDDI
-
Power supply terminal (+2.5V) (for core)
61
VSS
-
Ground terminal
62 to 69
QB2 to QB9
O
Video signal (blue) output to the HDMI panellink cinema transmitter
70
VDDI
-
Power supply terminal (+2.5V) (for core)
71
VSS
-
Ground terminal
72, 73
QG0, QG1
O
Video signal (green) output terminal Not used
74, 75
QG2, QG3
O
Video signal (green) output to the HDMI panellink cinema transmitter
76
VDDE
-
Power supply terminal (+3.3V) (for I/O)
77 to 80
OG4 to OG7
O
Video signal (green) output to the HDMI panellink cinema transmitter
81
VSS
-
Ground terminal
83
HCD-X1
Pin No.
Pin Name
I/O
Description
82, 83
OG8, OG9
O
Video signal (green) output to the HDMI panellink cinema transmitter
84, 85
QR0, QR1
O
Video signal (red) output terminal Not used
86 to 90
OR2 to OR6
O
Video signal (red) output to the HDMI panellink cinema transmitter
91
VSS
-
Ground terminal
92
OVDDE2
-
Power supply terminal (+3.3V) (for I/O)
93 to 95
OR7 to OR9
O
Video signal (red) output to the HDMI panellink cinema transmitter
96
QV
O
Vertical sync signal output to the HDMI panellink cinema transmitter
97
QH
O
Horizontal sync signal output to the HDMI panellink cinema transmitter
98
QDE
O
Dsata enable signal output to the HDMI panellink cinema transmitter
99
QCLK
O
Pixel clock signal output to the HDMI panellink cinema transmitter
100
VDDI
-
Power supply terminal (+2.5V) (for core)
101
VSS
-
Ground terminal
102
EXCLK
I
Pixel clock signal input terminal for external PLL mode
In internal PLL miode, must be fixed at "L" Fixed at "L" in this set
In internal PLL miode, must be fixed at "L" Fixed at "L" in this set
103
OVDDE3
-
Power supply terminal (+3.3V) (for I/O)
104
PH1
O
Phase comparate signal output terminal for external PLL (reference)
In internal PLL miode, must be not connected not connect in this set
In internal PLL miode, must be not connected not connect in this set
105
N.C.
-
Not used
106
AVS1
-
Ground terminal (for PLL)
107
AVD1
-
Power supply terminal (+3.3V) (for PLL)
108
CPO
O
Charge pump output terminal for internal PLL mode
109
N.C.
-
Not used
110
VCI
I
VCO input terminal for internal PLL mode
111
AVS2
-
Ground terminal (for PLL)
112
AVD2
-
Power supply terminal (+3.3V) (for PLL)
113
N.C.
-
Not used
114
PH2
O
Phase comparate signal output terminal for external PLL mode (feedback)
In internal PLL miode, must be not connected not connect in this set
In internal PLL miode, must be not connected not connect in this set
115
PLLEN
I
Selection terminal for internal PLL mode/external PLL mode
"L": internal PLL mode, "H": external PLL mode Fixed at "H" in this set
"L": internal PLL mode, "H": external PLL mode Fixed at "H" in this set
116
OVDDE4
-
Power supply terminal (+3.3V) (for I/O)
117
DCLK
I
System clock input (27 MHz) from the progressive scan converter
118
OVSS1
-
Ground terminal
119
DCLKP
I
Setting terminal for DCLK polarity
120
VDDI
-
Power supply terminal (+2.5V) (for core)
84
HCD-X1
MIB01 BOARD IC601 MB89538APFM-G-663-E1 (HDMI CONTROLLER)
Pin No.
Pin Name
I/O
Description
1, 2
P46, P47
-
Not used
3 to 10
AN0 to AN7
-
Not used
11
AVCC
-
Power supply terminal (+5.2V) (for internal A/D converer)
12
AVR
I
Reference voltage (+5.2V) input terminal (for internal A/D converer)
13
AVSS
-
Ground terminal (for internal A/D converer)
14
XSMCS
I
Chip select signal input from the servo DSP
15
INT11
-
Not used
16
XTXINT
I
Interrupt status input from the HDMI panellink cinema transmitter
17
INT13
-
Not used
18
P64
-
Not used
19
XRST
I
System reset signal input from the servo DSP "L": reset
20, 21
MOD0, MOD1
I
Setting terminal for memory access mode Fixed at "L" in this set
22
X0
I
System clock input terminal (8 MHz)
23
X1
O
System clock output terminal (8 MHz)
24
VSS
-
Ground terminal
25
P27
-
Not used
26
SDA1
I/O
Two-way data bus with the progressive scan converter and pixel resolution converter
27
SCL1
O
Serial data transfer clock signal output to the progressive scan converter and pixel resolution
converter
converter
28
P-CON
-
Not used
29, 30
P22, P23
-
Not used
31
SDA0
I/O
Two-way data bus with the HDMI panellink cinema transmitter
32
SCL0
O
Serial data transfer clock signal output to the HDMI panellink cinema transmitter
33, 34
N.C
-
Not used
35
XTXRST
O
System reset signal output to the HDMI panellink cinema transmitter "L": reset
36
XIPRST
O
System reset signal output to the progressive scan converter "L": reset
37
XSCRST
O
System reset signal output to the pixel resolution converter "L": reset
38, 39
N.C
-
Not used
40
DL-MODE
-
Not used
41 to 43
N.C
-
Not used
44, 45
TYPE0, TYPE1
-
Not used
46 to 49
N.C
-
Not used
50
SMSCK
-
Not used
51
SMSDI
I
Serial data transfer clock signal input from the servo DSP
52
SMSDO
O
Serial data output to the servo DSP
53
SI1
I
Serial data input from the servo DSP
54
PTO2
-
Not used
55
PWC
-
Not used
56
VCC
-
Power supply terminal (+5.2V)
57
WTO
-
Not used
58
PTO1
-
Not used
59
EC
-
Not used
60
SCK2
-
Not used
61
SDA
I/O
Two-way data bus terminal for the HDMI OUT jack
62
SCL
O
Serial data transfer clock signal output terminal for the HDMI OUT jack
63
UCK2
-
Not used
64
UD2
-
Not used
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