Sony DAV-X1 / HCD-X1 Service Manual ▷ View online
77
HCD-X1
Pin No.
Pin Name
I/O
Description
229
XTALI
I
System clock input terminal (27 MHz)
230
JITFO
O
Output terminal of the RF jitter meter
231
JITFN
I
Input terminal of the RF jitter meter
232
PLLVSS
-
Ground terminal
233
IDAC
-
Not used
234
PLLVDD3
-
Power supply terminal (+3.3V)
235
LPFON
O
Data PLL loop filter output terminal
236
LPFIP
I
Data PLL loop filter input terminal
237
LPFIN
I
Data PLL loop filter input terminal
238
LPFOP
O
Data PLL loop filter output terminal
239
VDD3
-
Power supply terminal (+3.3V)
240
VCM
-
Not used
241
VSS
-
Ground terminal
242
VREFP
-
For reference voltage terminal
243
VREFN
-
For reference voltage terminal
244
RFVDD3
-
Power supply terminal (+3.3V)
245
RFRPDC
O
RF ripple detect output terminal
246
RFRPAC
I
RF ripple detect input terminal
247
HRFZC
I
High frequency RF ripple zero crossing terminal
248
CRTPLP
O
Defect level filter capacitor connecting terminal
249
RFGND
-
Ground terminal
250
CEQP
-
Not used
251
CEQN
-
Not used
252
OSP
O
RF offset cancellation capacitor connecting terminal
253
OSN
O
RF offset cancellation capacitor connecting terminal
254
RFGC
O
RF AGC loop capacitor connecting for DVD-ROM
255
IREF
I
Reference current input terminal
256
AVDD3
-
Power supply terminal (+3.3V)
78
HCD-X1
MIB01 BOARD IC503 CXD9837R (PROGRESSIVE SCAN CONVERTER)
Pin No.
Pin Name
I/O
Description
1
OVDD
-
Power supply terminal (+3.3V) (for I/O)
2
CLK1
I
System clock input (27 MHz) from the servo DSP
3
TEST7
I
Terminal for test Fixed at "L" in this set
4
PLL EN
I
PLL enable signal input from the servo DSP
5, 6
PI0, PI1
-
Not used
7
PI2
I
Video data input from the servo DSP
8
PI3
I
Y signal input from the servo DSP
9
PI4
I
Chroma signal input from the servo DSP
10
PI5
I
Video signal input from the servo DSP
11
PI6
I
Chroma signal input from the servo DSP
12, 13
PI7, PI8
I
Component video signal input from the servo DSP
14
PI9
I
Video data input from the servo DSP
15
NHSI
I
Horizontal sync signal input from the servo DSP
16
NVSI
I
Vertical sync signal input from the servo DSP
17
OVSS
-
Ground terminal (for I/O)
18
THMD
I
Through mode setting terminal Fixed at "L" in this set
19
CVSS
-
Ground terminal (for core)
20
NVSO
O
Vertical sync signal output terminal Not used
21
NHSO
O
Horizontal sync signal output terminal Not used
22 to 25
PO9 to PO6
O
Video signal output to the video encoder and pixel resolution converter
26
OVDD
-
Power supply terminal (+3.3V) (for I/O)
27
OVSS
-
Ground terminal (for I/O)
28 to 31
PO5 to PO2
O
Video signal output to the video encoder and pixel resolution converter
32, 33
PO1, PO0
O
Video signal output to the pixel resolution converter
34
TEST0
I
Terminal for test Fixed at "L" in this set
35
OVSS
-
Ground terminal (for I/O)
36
OVDD
-
Power supply terminal (+3.3V) (for I/O)
37
CVDD
-
Power supply terminal (+2.5V) (for core)
38
TEST1
I
Terminal for test Fixed at "L" in this set
39
TEST2
I
Terminal for test Fixed at "L" in this set
40
CLKO
O
System clock output (27 MHz) to the video encoder and pixel resolution converter
41 to 45
YO9 to YO5
O
Video signal output to the video encoder and pixel resolution converter
46
OVDD
-
Power supply terminal (+3.3V) (for I/O)
47
OVSS
-
Ground terminal (for I/O)
48 to 52
YO4 to YO0
O
Video signal output to the video encoder and pixel resolution converter
53
OVDD
-
Power supply terminal (+3.3V) (for I/O)
54
CVSS
-
Ground terminal (for core)
55
OVSS
-
Ground terminal (for I/O)
56 to 60
CO0 to CO4
O
Video signal output to the video encoder and pixel resolution converter
61
OVDD
-
Power supply terminal (+3.3V) (for I/O)
62
OVSS
-
Ground terminal (for I/O)
63 to 67
CO5 to CO9
O
Video signal output to the video encoder and pixel resolution converter
68
FILM
O
Filim sequence detection flag output terminal Not used
69
RFFI
I
MPEG flag (repeat first field flag) input terminal Not used
70
OVSS
-
Ground terminal (for I/O)
71
CVDD
-
Power supply terminal (+2.5V) (for core)
79
HCD-X1
Pin No.
Pin Name
I/O
Description
72
IVDD
-
Power supply terminal (+3.3V) (for I/O)
73
OVDD
-
Power supply terminal (+3.3V) (for I/O)
74 to 77
MD19 to MD16
I/O
Two-way data bus terminal Not used
78
OVDD
-
Power supply terminal (+3.3V) (for I/O)
79
OVSS
-
Ground terminal (for I/O)
80 to 83
MA3, MA4,
MA2, MA5
O
Address signal output to the SD-RAM
84
OVDD
-
Power supply terminal (+3.3V) (for I/O)
85
OVSS
-
Ground terminal (for I/O)
86 to 89
MA1, MA6,
MA0, MA7
O
Address signal output to the SD-RAM
90
OVSS
-
Ground terminal (for I/O)
91
IVSS
-
Ground terminal (for I/O)
92
CVSS
-
Ground terminal (for core)
93
OVDD
-
Power supply terminal (+3.3V) (for I/O)
94 to 97
MA10, MA8,
MA11, MA9
O
Address signal output to the SD-RAM
98
OVDD
-
Power supply terminal (+3.3V) (for I/O)
99
OVSS
-
Ground terminal (for I/O)
100
RAS
O
Row address strobe signal output to the SD-RAM
101
DQM
O
Data mask signal output to the SD-RAM
102
CAS
O
Column address strobe signal output to the SD-RAM
103
MCLK
O
Serial data transfer clock signal output to the SD-RAM
104
WE
O
Write enable signal output to the SD-RAM
105
TEST3
I
Terminal for test Fixed at "L" in this set
106
TEST4
I
Terminal for test Fixed at "L" in this set
107
OVSS
-
Ground terminal (for I/O)
108
OVDD
-
Power supply terminal (+3.3V) (for I/O)
109
CVDD
-
Power supply terminal (+2.5V) (for core)
110 to 113
MD7, MD8,
MD6, MD9
I/O
Two-way data bus with the SD-RAM
114
OVDD
-
Power supply terminal (+3.3V) (for I/O)
115
OVSS
-
Ground terminal (for I/O)
116 to 119
MD5, MD10,
MD4, MD11
I/O
Two-way data bus with the SD-RAM
120
OVDD
-
Power supply terminal (+3.3V) (for I/O)
121
OVSS
-
Ground terminal (for I/O)
122 to 125
MD3, MD12,
MD2, MD13
I/O
Two-way data bus with the SD-RAM
126
OVSS
-
Ground terminal (for I/O)
127
CVSS
-
Ground terminal (for core)
128
OVDD
-
Power supply terminal (+3.3V) (for I/O)
129 to 132
MD1, MD14,
MD0, MD15
I/O
Two-way data bus with the SD-RAM
133
SLV
I
MPU interface slave address setting terminal
Slave address setting: 0 x 72 when SLV is "0", 0 x 70 when SLV is "1"
Slave address setting: 0 x 72 when SLV is "0", 0 x 70 when SLV is "1"
134
RFFO
O
MPEG flag (repeat first field flag) outnput terminal Not used
135
SDA
I/O
Two-way data bus with the HDMI controller
136
SCL
I
Serial data transfer clock signal input from the HDMI controller
80
HCD-X1
Pin No.
Pin Name
I/O
Description
137
SRN
I
System reset signal input from the HDMI controller "L": reset
138
OVSS
-
Ground terminal (for I/O)
139
CVDD
-
Power supply terminal (+2.5V) (for core)
140
PLL VDD
-
Power supply terminal (+2.5V) (for PLL)
141
VPDX
-
Not used
142
TEST6
I
Terminal for test Fixed at "L" in this set
143
OVSS
-
Ground terminal (for I/O)
144
IVDD
-
Power supply terminal (+3.3V) (for I/O)
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