Sony DAV-EA20 / HCD-EA20 Service Manual ▷ View online
73
HCD-EA20
• IC701 CXD1882R (DVD DECODER)(DMB03 BOARD)
Pin No.
1, 2
3
4
5
6
7
8
9 to 14
15
16
17
18
19
20, 21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
I/O
I/O
—
I/O
I
—
I
—
I
—
O
I
I
I
O
—
I
O
—
O
O
—
O
O
O
O
—
O
O
—
O
—
O
O
O
—
O
O
O
O
—
O
O
—
O
—
I
O
O
I
Pin Name
D5, D6
VSS
D7
A0
VDD
A1
VDD5V
A2 to A7
VSS
XWAIT
XRD
XWR
XCS
XINT0, XINT1
VDD
XHRS
HDB7
VSS
HDB8
HDB6
VDDS
HDB9
HDB5
HDBA
HDB4
VSS
HDBB
HDB3
VDD
HDBC
VDDS
HDB2
HDBD
HDB1
VSS
HDBE
HDB0
HDBF
XSAK
VDDS
XDCK
XSHD
VDD
REDY
VSS
XSRQ
HINT
XS16
HA1
Description
Two-way data bus with the mechanism controller
Ground terminal (digital system)
Two-way data bus with the mechanism controller
Address signal input from the mechanism controller
Power supply terminal (+3.3V) (digital system)
Address signal input from the mechanism controller
Power supply terminal (+5V)
Address signal input from the mechanism controller
Ground terminal (digital system)
Wait signal output terminal Not used
Read strobe signal input from the mechanism controller
Write strobe signal input from the mechanism controller
Chip select signal input from the mechanism controller
Interrupt signal output to the mechanism controller
Power supply terminal (+3.3V) (digital system)
Not used
Stream data signal output to the DSD decoder and DVD system processor
Ground terminal (digital system)
Error flag signal output to the DSD decoder and DVD system processor
Stream data signal output to the DSD decoder and DVD system processor
Power supply terminal (+5V) (digital system)
Not used
Stream data signal output to the DSD decoder and DVD system processor
Not used
Stream data signal output to the DSD decoder and DVD system processor
Ground terminal (digital system)
Not used
Stream data signal output to the DSD decoder and DVD system processor
Power supply terminal (+3.3V) (digital system)
Not used
Power supply terminal (+5V) (digital system)
Stream data signal output to the DSD decoder and DVD system processor
Not used
Stream data signal output to the DSD decoder and DVD system processor
Ground terminal (digital system)
Not used
Stream data signal output to the DSD decoder and DVD system processor
Not used
Serial data effect flag signal output to the DSD decoder and DVD system processor
Power supply terminal (+5V) (digital system)
Serial data transfer clock signal output to the DSD decoder and DVD system processor
Header flag signal output to the DSD decoder
Power supply terminal (+3.3V) (digital system)
Not used
Ground terminal (digital system)
“DVD mode: Serial data request signal input from the DVD system processor
SACD mode: Serial data request signal input from the DSD decoder”
SACD mode: Serial data request signal input from the DSD decoder”
Not used
Not used
Not used
74
HCD-EA20
Pin No.
57
58
59, 60
61
62, 63
64
65
66 to 69
70
71
72
73 to 75
76
77
78
79, 80
81
82 to 87
88
89
90
91
92
93
94
95
96, 97
98
99
100
101, 102
103
104 to 106
107
108
109
110
111
112
113, 114
115
116
117
118, 119
120
121
122, 123
124
125
126, 127
Pin Name
XPDI
VDDS
HA0, HA2
VSS
HCS0, HCS1
VDD
DASP
MDB0 to MDB3
VSS
MDB4
VDD5V
MDB5 to MDB7
XMWR
VDD
XRAS
MA0, MA1
VSS
MA2 to MA7
VDD
MA8
VSS
MA9
MNT1
MNT2
XMOE
XCAS
MDB8, MDB9
VSS
MDBA
VDD
MDBB, MDBC
VDD5V
MDBD to MDBF
GFS
VSS
APEO
VDD
DASYO
GNDA5
ASF1, AFS2
DASYI
RFDCC
RFIN
VCCA5, VCCA4
VCOR1
VCOIN
GNDA4, GNDA3
LPF5
VC1
LPF2, LPF1
I/O
I/O
—
I
—
I
—
I/O
I/O
—
I/O
—
I/O
O
—
O
O
—
O
—
O
—
O
O
O
O
O
I/O
—
I/O
—
I/O
—
I/O
O
—
O
—
O
—
—
I
I
I
—
—
I
—
O
I
I
Description
Not used
Power supply terminal (+5V) (digital system)
Not used
Ground terminal (digital system)
Not used
Power supply terminal (+3.3V) (digital system)
Not used
Two-way data bus with the D-RAM
Ground terminal (digital system)
Two-way data bus with the D-RAM
Power supply terminal (+5V)
Two-way data bus with the D-RAM
Write enable signal output to the D-RAM
Power supply terminal (+3.3V) (digital system)
Row address strobe signal output to the D-RAM
Address signal output to the D-RAM
Ground terminal (digital system)
Address signal output to the D-RAM
Power supply terminal (+3.3V) (digital system)
Address signal output to the D-RAM
Ground terminal (digital system)
Address signal output to the D-RAM
EEPROM ready signal output to the mechanism controller
Operation clock signal output for PSP physical disc mark detection to DSD decoder
Output enable signal output to the D-RAM
Column address strobe signal output to the D-RAM
Two-way data bus with the D-RAM
Ground terminal (digital system)
Two-way data bus with the D-RAM
Power supply terminal (+3.3V) (digital system)
Two-way data bus with the D-RAM
Power supply terminal (+5V)
Two-way data bus with the D-RAM
Guard frame sync signal output to the mechanism controller
Ground terminal (digital system)
Absolute phase error signal output
Power supply terminal (+3.3V) (digital system)
RF binary signal output
Ground terminal (analog system)
Filter connected terminal for selection the constant asymmetry compensation
Analog signal input after integrated from the RF binary signal
Input terminal for adjusting DC cut high-pass filter for RF signal Not used
RF signal input from the DVD/CD RF amplifier
Power supply terminal (+3.3V) (analog system)
VCO oscillating range setting resistor connected terminal
VCO input terminal
Ground terminal (analog system)
Signal output from the operation amplifier from PLL loop filter
Middle point voltage (+1.65V) input terminal
Inverted signal input to the operation amplifier from PLL loop filter
75
HCD-EA20
Pin No.
128, 129
130
131
132
133, 134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172 to 176
Pin Name
VCCA3, VCCA2
PD0
PDHVCC
FDO
GNDA2, GNDA1
SPO
VC2
MDIN2
MDIN1
VCCA1
CLVS
VSS
MDSOUT
VDD
MDPOUT
DEFECT
GSCOR
EXCK
SBIN
VSS
SCOR
WFCK
VDD5V
XRCI
VDDS
C2PO
VDD
DBCK
BCLK
DDAT
MDAT
VSS
DLRC
LRCK
XRST
IFS0
IFS1
XTAL
VSS
XTL2
XTL1
VDD
D0 to D4
I/O
—
O
I
O
—
O
I
I
I
—
O
—
O
—
O
I
I
O
I
—
I
I
—
I
—
I
—
O
I
O
I
—
O
I
I
I
I
I
—
O
I
—
I/O
Description
Power supply terminal (+3.3V) (analog system)
Signal output from the charge pump for phase comparator
Middle point voltage input terminal for RF PLL
Signal output from the charge pump for frequency comparator
Ground terminal (analog system)
Spindle motor control signal output
Middle point voltage (+1.65V) input terminal
Spindle motor servo drive signal input
MDP input terminal
Power supply terminal (+3.3V) (analog system)
Control signal output for selection the spindle control filter constant at CLVS
Ground terminal (digital system)
Frequency error output terminal of internal CLV circuit
Power supply terminal (+3.3V) (digital system)
Phase error output terminal of internal CLV circuit
Defect signal input terminal (conected to ground terminal)
Guard subcode sync (S0+S1) detection signal input from the digital signal processor
Subcode serial data reading clock signal output to the digital signal processor
Subcode serial data input from the digital signal processor
Ground terminal (digital system)
Subcode sync (S0+S1) detection signal input from the digital signal processor
Write frame clock signal input from the digital signal processor
Power supply terminal (+5V)
RAM overflow signal input terminal (conected to ground terminal)
Power supply terminal (+5V) (digital system)
C2 pointer signal input from the digital signal processor
Power supply terminal (+3.3V) (digital system)
Bit clock signal (2.8224 MHz) output terminal Not used
Bit clock signal (2.8224 MHz) input from the digital signal processor
PCM data output terminal
Serial data input from the digital signal processor
Ground terminal (digital system)
L/R sampling clock signal (44.1 kHz) output terminal Not used
L/R sampling clock signal (44.1 kHz) input from the digital signal processor
Reset signal input from the mechanism controller “L”: reset
Interface selection signal input terminal Fixed at “L” in this set
Interface selection signal input terminal Fixed at “H” in this set
33.8688 MHz clock signal input terminal
Ground terminal (digital system)
System clock output terminal (33.8688 MHz)
System clock input terminal (33.8688 MHz)
Power supply terminal (+3.3V) (digital system)
Two-way data bus with the mechanism controller
76
HCD-EA20
• IC901 CXP973064-232R (MECHANISM CONTROLLER)(DMB03 BOARD)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14 to 21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43, 44
45
46
47
48
49
50
51
52
53
54
55
56
I/O
O
O
O
O
I/O
I
O
O
I
O
O
O
—
I/O
I
I
O
O
I
O
O
I
I
I
O
I
O
O
O
O
I
—
I
O
—
O
O
O
I
I
O
O
O
I
O
O
—
I
Pin Name
NO USE
SDEN
DOCTRL/
ISBTEST
XPST 2753
SDA EEP
MNT1
FCS JMP 1
FCS JMP 2
SENS CD
CDSP2
CDSP4
XCS DVD
VSS
D0 to D7
INIT0 DVD
INIT1 DVD
MSCK SAMBA
XRST 1882
SCOR
LAT CD
LD ON
MIRR
COUT CD
INLIM
CS ZIVA
SI ZIVA
SO ZIVA
SCK ZIVA
DRVIRQ
DRVRDY
RST
VSS
XTAL
EXTAL
VDD
SLED A, SLED B
SCK DSD
SDOUT DSD
SDIN DSD
READY DSD
DATA CD
CLOK CD
XMSLAT
SQSO
MUTE DSD
SQCK
VSS
CONTROL 4
Description
Not used
Serial data enable signal output to DVD/CD RF amplifier
Digital out on/off control signal output to the digital signal processor
“L”: digital out off, “H”: digital out on
“L”: digital out off, “H”: digital out on
Reset signal output for DSD decoder
Two-way data bus with the EEPROM
EEPROM ready signal input from the DVD decoder
Focus jump 1 signal output to the motor/coil driver
Focus jump 2 signal output to the motor/coil driver
Internal status (SENSE) signal input from the digital signal processor
Loading motor drive signal (loading in direction) output terminal
Loading motor drive signal (loading out direction) output terminal
Chip select signal output to the DVD decoder
Ground terminal (digital system)
Two-way data bus with the DVD decoder
Interrupt signal input from the DVD decoder
Interrupt signal input from the DVD decoder
Serial data transfer clock signal output to the DSD decoder
Reset signal output to the DVD decoder “L”: reset
Subcode sync (S0+S1) detection signal input from the digital signal processor
Serial data latch pulse signal output to the digital signal processor
Laser diode on/off control signal output to the DVD/CD RF amplifier
“L”: laser diode off, “H”: laser diode on
“L”: laser diode off, “H”: laser diode on
Mirror signal input from the digital signal processor
Numbers of track counted signal input from the digital signal processor
Detection signal input from limit in switch The optical pick-up is inner position when “H”
Chip select signal output to the DVD system processor
Serial data input from the DVD system processor
Serial data output to the DVD system processor
Serial data transfer clock signal output to the DVD system processor
Interrupt request signal output to the DVD system processor
Ready signal output to the DVD system processor
System reset signal input from the DVD system processor “L”: reset
Ground terminal (digital system)
System clock input terminal (20 MHz)
System clock output terminal (20 MHz)
Power supply terminal (+3.3V) (digital system)
Sled motor drive signal output
Output terminal for offset adjustment of APEO
Serial data output to the DSD decoder
Serial data input from the DSD decoder
Ready signal input from the DSD decoder “L”: ready
Serial data output to the digital signal processor
Serial data transfer clock signal output to the digital signal processor
Serial data latch pulse signal output to the DSD decoder
Subcode Q data input from the digital signal processor
Muting on/off control signal output to the DSD decoder “H”: muting on
Subcode Q data reading clock signal output to the digital signal processor
Ground terminal (digital system)
Disc tray in detection signal input terminal Not used
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