Sony DAV-EA20 / HCD-EA20 Service Manual ▷ View online
65
HCD-EA20
ANALOG
DIGIT
AL
RCLK
NC
XO
XI
VSS2
T2
VDD2
T1
QUAL
RDA
T
VREF
MUX
VDD1
VSS1
VSS3
CMP
1
4
3
6
5
8
7
2
14
15
16
13
12 11 10
9
CLOCK
PLL 57kHz
RDS/ARI
COMPARATOR
8th SWITCHED
CAPACITOR
FILTER
ANTI-ALIASING
FILTER
BIPHASE
DECODER
PLL
1187.5Hz
DEFFERENTIAL
DECODER
TEST
– PANEL BOARD –
IC802 PT6315
IC291 BU1924F-E2
1
2
3
4
5
4-bit latch
24-bit output latch
12-bit shift register
Data selector
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Serial
interface
OSC
Timing generator
key scan
Display memory
24 bits x 12 words
Key data memory
(2 x 16 bits)
Command decoder
segment driver
Grid driver
Multiplexed driver
39
40
41
42
43
44
LED1
LED2
LED3
LED4
OSC
DOUT
DIN
CLK
STB
KEY1
KEY2
VSS
VDD
SEG1/KS1
SEG2/KS2
SEG3/KS3
SEG4/KS4
SEG5/KS5
SEG6/KS6
SEG7/KS7
SEG8/KS8
SEG9/KS9
SEG10/KS10
SEG20/GRID9
SEG21/GRID8
SEG22/GRID7
SEG23/GRID6
SEG24/GRID5
GRID4
GRID3
GRID2
GRID1
VDD
VSS
SEG11/KS11
SEG12/KS12
SEG13/KS13
SEG14/KS14
SEG15/KS15
SEG16/KS16
VEE
SEG17/GRID12
SEG18/GRID11
SEG19/GRID10
66
HCD-EA20
IC001 CXD1881AR
– RF BOARD –
MUX
ATT
INPUT
BIAS
AGC
GCA
PROGRAMMABLE
EQUALIZER
FILTER
DIFFERENTIATOR
64 63
62 61 60 59
58
57
51
56
1
2
FULL WAVE
RECTIFER
AGC CHARGE
PUMP
+
–
+
–
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
–
–
+
–
–
+
–
–
INPUT
SEL
ATT
2
4
2
2
INPUT
IMPEDANCE
SEL
OFFSET
CANSEL
MNTR
CONTROL
SERIAL
PORT
REGISTER
4
FROM
S-PORT
4
FROM
S-PORT
INPUT
IMPEDANCE
SEL
3
FROM
S-PORT
CLAMP &
ENVELOPE
LEVEL
DAC
SIGDET
AGCO
BUFFER
55 54
53 52
50
49
OUTPUT
INHIBIT
FROM S-PORT
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
GCA
CD/DVD
4
FROM
S-PORT
3
FROM
S-PORT
MUX
3
FROM
S-PORT
GCA
3
FROM
S-PORT
3
FROM
S-PORT
EQ
VC
COMPARATOR
PHASE
DETECTOR
PHASE
DETECTOR
A+D
B+D
+
+
+
A+C
B+C
GCA
W/LPF
SUM
AMP
AMP
18 19 20
21 22
24 25
23
26
27
28 29
31
32
30
GCA
GCA
VCI FOR SERVO INPUT
VC = VPB/2
DUAL APC
LD H/L
FROM S-PORT
APC SEL
DVD/CD
TOPHOLD
GCA
TOPHOLD
GCA
41
48
47
46
45
GCA
OFFSET
CANSEL
5
FROM
S-PORT
GCA
40
GCA
OFFSET
CANSEL
6
FROM
S-PORT
3
FROM
S-PORT
GCA
GCA
CEFDB
CP/CN
LOW
IMPEDANCE
CD/DVD
SUB
GCA
MUX
GCA
LPF
GCA
LPF
39
38
37
36
OFFSET
CANSEL
PEAK/BOTTOM
HOLD
BOTTOM
ENVELOPE
INPUT
BUFFER
5
FROM
S-PORT
GCA
LPF
V25/2
TE
RST
35
34
33
FOR SERVO
OUTPUT
PH
TOP
HOLD
GCA
SEL
LINKEN
MUX
HOLDEN
+
–
+
–
COMPA-
RATOR
INTERNAL
FDGHG
HYSTERESISTER
& OFFSET
FROM S-PORT
MIRR
COMPARATOR
COMPARATOR
INPUT GAIN
FROM S-PORT
SEL
DAC
SINK CURRENT
FROM S-PORT
2
AGCO
FAST ATTACK
AGC
HOLD
BCA
DET
DET
2
FROM
S-PORT
PH
2
2
INPUT
IMPEDANCE
FROM S-PORT
44
43
42
V33 FOR
OUTPUT
OUTPUT
BUFFER
PI
FE
TE
CE
V25
V125
V25/3
LPF ATT
POL SEL
BUFFER
CONTROL
SIGNALS
TO EACH
BLOCK
3
CE ATT
CEPOL
D
C
B
A
CD F
CD E
VPB
VC
DVDLD
CDLD
CDPD
DVDPD
LDON
VNB
MIRR
MP
MB
MIN
MEVO
MLPF
CE
SDEN
SDATA
SCLK
V33
FE
TE
PI
V25
V125
TPH
DFT
LINK
LCP
LCN
MNTR
DVDRFP
DVDRFN
A2
B2
C2
D2
CP
CN
D
C
B
A
CD D
CD C
CD B
CD A
RFDC
RFSIN
ATOP
ATON
AIN
AIP
VPA
RFAC
VNA
BYP
DIN
DIP
FNP
FNN
MEV
RX
67
HCD-EA20
VOUT
GND
SUB
TC
VCC
4
3
2
1
5
IC681 PST9229NL
– UCOM BOARD –
68
HCD-EA20
6-28. IC PIN FUNCTION DESCRIPTION
• IC207 ZIVA5X-C1F (DVD SYSTEM PROCESSOR)(DMB03 BOARD)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
I/O
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
—
I/O
I/O
I/O
I/O
I/O
I/O
—
—
I/O
I/O
I
I/O
I/O
I/O
I/O
—
—
—
—
O
O
O
O
O
O
O
O
O
O
—
—
O
O
O
O
O
O
Pin Name
VDDP
HA1
HD15
HD14
HD13
HD12
HD11
HD10
HD9
HD8
HD7
VDDP
GNDP
HD6
HD5
HD4
HD3
HD2
HD1
VDDP
GNDP
HD0
HDTACK
HIRQ0
WEH.UDS
WEL.LDS
HREAD
GPIO0
GND
VDD
GND25
VDD25
MA9
MA8
MA7
MA6
MA5
MA4
MA3
MA2
MA1
MA0
GND25
VDD25
MA10
MA11
BA1
BA0
MCS0
MCS1
Description
Power supply terminal (+3.3V) (I/O signal)
Address bus
Data bus (address signal multiplexed)
Data bus (address signal multiplexed)
Data bus (address signal multiplexed)
Data bus (address signal multiplexed)
Data bus (address signal multiplexed)
Data bus (address signal multiplexed)
Data bus (address signal multiplexed)
Data bus (address signal multiplexed)
Data bus (address signal multiplexed)
Power supply terminal (+3.3V) (I/O signal)
Ground terminal (I/O signal)
Data bus (address signal multiplexed)
Data bus (address signal multiplexed)
Data bus (address signal multiplexed)
Data bus (address signal multiplexed)
Data bus (address signal multiplexed)
Data bus (address signal multiplexed)
Power supply terminal (+3.3V) (I/O signal)
Ground terminal (I/O signal)
Data bus (address signal multiplexed)
Acknowledge signal input/output for host data transfer (not used)
Interrupt signal input for Medusa (not used)
Host upper data strobe signal output
Host lower data strobe signal output (not used)
Read/write strobe signal output
Jig detection port (pull-up)
Ground terminal (inside core)
Power supply terminal (+1.8V) (inside core)
Ground terminal (SDRAM I/O signal)
Power supply terminal (+3.3V) (SDRAM I/O signal)
SDRAM address bus
SDRAM address bus
SDRAM address bus
SDRAM address bus
SDRAM address bus
SDRAM address bus
SDRAM address bus
SDRAM address bus
SDRAM address bus
SDRAM address bus
Ground terminal (SDRAM I/O signal)
Power supply terminal (+3.3V) (SDRAM I/O signal)
SDRAM address bus
SDRAM address bus
SDRAM bank select 1 signal output
SDRAM bank select 0 signal output
SDRAM chip select 0 signal output
Not used
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