Sony CX-JTV8 / JAX-TV8 Service Manual ▷ View online
53
CX-JTV8
6-27.
IC PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
I/O
Description
1
VB
O
Connected to ground via a capacitor
2
IREF
O
D/A converter reference current output terminal
3
VRF
I
D/A converter reference voltage input terminal
4
VG
O
Connected to the analog power supply (+2.5V) via a capacitor
5
XCPSIG
O
Luminance video composite/component signal invert output terminal Not used
6
CPSIG
O
Luminance video composite/component signal output terminal
7
NC
—
Not used
8
V AVD2
—
Analog power supply terminal (+2.5V) (for D/A converter)
9
V AVS2
—
Analog ground terminal (for D/A converter)
10
IVD1
—
Power supply terminal (+3.3V) (for I/O)
11
I2C CLK
I/O
Communication data reading clock signal input or transfer clock signal output terminal
Not used
Not used
12
I2C DATA
I/O
Communication data bus terminal Not used
13
GPIO0
I
Serial data input from the system controller
14
GPIO1
O
Serial data output to the system controller
15
GPIO2
O
Serial data transfer clock signal output to the system controller
16
GPIO3
I
Request signal input from the system controller
17
LVD1
—
Digital power supply terminal (+2.5V) (for AV decoder block)
18
GPIO4
I
Acknowledge signal input from the system controller
19
GPIO5
O
Chip select signal output to the system controller
20, 21
GPIO6, GPIO7
I/O
Not used
22
LVS1
—
Digital ground terminal (for AV decoder block)
23
GPIO8
I/O
Not used
24
GPIO9
O
Frequency selection signal output terminal
25
GPIO10
I/O
Not used
26
GPIO11
O
Serial data latch pulse signal output to the digital filter
27
LVD2
—
Digital power supply terminal (+2.5V) (for AV decoder block)
28
GPIO12
O
Control signal output to the D/A converter
29
GPIO13
O
Serial data transfer clock signal output to the digital filter and D/A converter
30
GPIO14
O
Serial data output to the digital filter and D/A converter
31
IVS1
—
Ground terminal (for I/O)
32
LVS2
—
Digital ground terminal (for AV decoder block)
33
IVD2
—
Power supply terminal (+3.3V) (for I/O)
34 to 37
DRADR0 to
DRADR3
O
Address signal output to the D-RAM and program ROM
38
LVD3
—
Digital power supply terminal (+2.5V) (for AV decoder block)
39 to 45
DRADR4 to
DRADR10
O
Address signal output to the D-RAM and program ROM
46
LVS3
—
Digital ground terminal (for AV decoder block)
47
IVS2
—
Ground terminal (for I/O)
48
IVD3
—
Power supply terminal (+3.3V) (for I/O)
49 to 56
DRDAT0 to
DRDAT7
I/O
Two-way data bus with the D-RAM Data input from the program ROM
57
IVS3
—
Ground terminal (for I/O)
58
IVD4
—
Power supply terminal (+3.3V) (for I/O)
•
VMP42DN BOARD IC505 CXD1887R (DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR,
MPEG VIDEO/AUDIO DECODER, VIDEO SIGNAL ENCODER)
54
CX-JTV8
Pin No.
Pin Name
I/O
Description
59 to 66
DRDAT8 to
DRDAT15
I/O
Two-way data bus with the D-RAM Data output to the program ROM
67
IVS4
—
Ground terminal (for I/O)
68
DRCAS
O
Column address strobe signal output to the D-RAM
69
LVD4
—
Digital power supply terminal (+2.5V) (for AV decoder block)
70
DRCK
O
Clock signal output to the D-RAM
71
IVD5
—
Power supply terminal (+3.3V) (for I/O)
72
DRRAS
O
Row address strobe signal output to the D-RAM
73
DRWEL
O
Write enable signal output to the D-RAM
74
NVOEL
O
Chip select signal output to the D-RAM
75
LVS4
—
Digital ground terminal (for AV decoder block)
76
DRBS
O
Bank select signal output to the D-RAM
77, 78
DRDQM0,
DRDQM1
O
Mask control signal output to the D-RAM
79
IVS5
—
Ground terminal (for I/O)
80
NC
—
Not used
81
SYSRST
I
Reset signal input from the system controller “L”: reset
82
IRDIN
I
IR data input terminal Not used
83
NC
—
Not used
84
VDD1
—
Digital power supply terminal (+2.5V) (for CD-DSP block)
85
V16M
O
Wide-band EFM PLL VCO2 oscillation output terminal Not used
86
DOUT
O
Digital audio signal output terminal Not used
87
L CDLRCK
I
L/R sampling clock signal (44.1 kHz) input terminal
88
LRCK
O
L/R sampling clock signal (44.1 kHz) output terminal
89
VSS1
—
Digital ground terminal
90
L CDDATA
I
Serial data input terminal
91
PCMD
O
Serial data output terminal
92
L CDBCK
I
Bit clock signal (2.8224 MHz) input terminal
93
BCK
O
Bit clock signal (2.8224 MHz) output terminal
94
EMPH
O
“L” is output when playback disc is emphasis off
“H” is output when playback disc is emphasis on Not used
“H” is output when playback disc is emphasis on Not used
95
L SQSO
I
Subcode-Q 80-bit, PCM peak and level data, CD text data input terminal
96
SQSO
O
Subcode-Q 80-bit, PCM peak and level data, CD text data output terminal
97
VDD2
—
Digital power supply terminal (+2.5V) (for CD-DSP block)
98
L SQCK
O
SQSO readout clock signal output terminal
99
SQCK
I
SQSO readout clock signal input terminal
100
SBSO
O
Subcode P to W serial data output terminal Not used
101
EXCK
I
SBSO readout clock signal input terminal Not used
102
DATA
I
Serial data input terminal
103
L DDAT
O
Serial data output terminal
104
VSS2
—
Digital ground terminal
105
L CDXRST
O
Reset signal output terminal “L”: reset
106
XRST
I
Reset signal input terminal “L”: reset
107
MUTE
I
Muting on/off control signal input terminal “H”: muting on Not used
108
L XLAT
O
Serial data latch pulse signal output terminal
55
CX-JTV8
Pin No.
Pin Name
I/O
Description
109
XLAT
I
Serial data latch pulse signal input terminal
110
L DCLK
O
Serial data transfer clock signal output terminal
111
CLOK
I
Serial data transfer clock signal input terminal
112
L SENS
I
SENS signal input terminal
113
SENS
O
SENS signal output terminal
114
L SLCK
O
SENS serial data readout clock signal output terminal
115
SCLK
I
SENS serial data readout clock signal input terminal
116
VDD3
—
Digital power supply terminal (+2.5V) (for CD-DSP block)
117
ATSK
I/O
Input/output terminal for anti-shock Not used
118
XUGF
O
XUGF signal output terminal Not used
119
XPCK
O
XPCK signal output terminal Not used
120
L GFS
I
Guard frame sync signal input terminal
121
GFS
O
Guard frame sync signal output terminal
122
VSS3
—
Digital ground terminal
123
L CDC2PO
I
C2 pointer signal input terminal
124
C2PO
O
C2 pointer signal output terminal
125
L SCOR
I
Subcode sync (S0+S1) detection signal input terminal
126
SCOR
O
Subcode sync (S0+S1) detection signal output terminal
127
COUT
O
Numbers of track counted signal output terminal Not used
128
VDD4
—
Digital ground terminal (for CD-DSP block)
129
MIRR
I/O
Mirror signal input/output terminal Not used
130
DFCT
I/O
Defect signal input/output terminal Not used
131
L FOK
I/O
Focus OK signal input/output terminal
132
FOK
I/O
Focus OK signal input/output terminal
133
MDP
O
Spindle motor servo drive signal output terminal
134
VSS4
—
Digital ground terminal
135
SSTP
I
Detection signal input from limit in switch The optical pick-up is inner position when “H”
136
FSTO
O
2/3 frequency-division output of the XTAI (pin <zv. ) Not used
137
SFDR
O
Sled motor servo drive signal (+) output terminal
138
SRDR
O
Sled motor servo drive signal (–) output terminal
139
VDD5
—
Digital power supply terminal (+2.5V) (for CD-DSP block)
140
TFDR
O
Tracking coil servo drive signal (+) output terminal
141
TRDR
O
Tracking coil servo drive signal (–) output terminal
142
FFDR
O
Focus coil servo drive signal (+) output terminal
143
FRDR
O
Focus coil servo drive signal (–) output terminal
144
VSS5
—
Digital ground terminal
145
WFCK
O
Write frame clock signal output terminal Not used
146
WDCK
O
Word clock signal output terminal Not used
147
ASYE
I
Asymmetry circuit on/off control signal input terminal “L”: off, “H”: on Not used
148
VDD6
—
Digital power supply terminal (+2.5V) (for CD-DSP block)
149
XTAI
I
Main system clock input terminal (33.8688 MHz)
150
XTAO
O
Main system clock output terminal (33.8688 MHz)
151
VSS6
—
Digital ground terminal
152
TES1
I
Input terminal for the test Normally: fixed at “L”
153
TEST
I
Input terminal for the test Normally: fixed at “L”
56
CX-JTV8
Pin No.
Pin Name
I/O
Description
154, 155
NC
—
Not used
156
AVD0
—
Analog power supply terminal (+2.5V)
157
IGEN
I
Operational amplifier constant current input terminal
158
AVS0
—
Analog ground terminal
159
ADIO
O
Output terminal for the test Not used
160
RFDC
I
RF signal input from the RF amplifier
161
CE
I
Center servo analog signal input terminal
162
TE
I
Tracking error signal input from the RF amplifier
163
SE
I
Sled error signal input from the RF amplifier
164
FE
I
Focus error signal input from the RF amplifier
165
VC
I
Center voltage (+1.65V) input terminal
166
VPCO
O
Wide-band EFM PLL charge pump output terminal
167
VCTL
I
Wide-band EFM PLL VCO2 control voltage input terminal
168
FILO
O
Master PLL filter output terminal
169
FILI
I
Master PLL filter input terminal
170
PCO
O
Master PLL charge pump output terminal
171
CLTV
I
Multiplier VCO1 control voltage input terminal
172
AVS1
—
Analog ground terminal
173
RFAC
I
EFM signal input from the RF amplifier
174
BIAS
I
Asymmetry circuit constant current input terminal
175
ASYI
I
Asymmetry comparator voltage input terminal
176
ASYO
O
EFM full-swing output terminal
177
AVD1
—
Analog power supply terminal (+2.5V)
178
VDD7
—
Digital power supply terminal (+2.5V) (for CD-DSP block)
179
SOUT
O
Serial data output terminal Not used
180
SOCK
O
Serial data readout clock signal output terminal Not used
181
XOLT
O
Serial data latch pulse signal output terminal Not used
182
C4M
O
4.2336 MHz clock signal output terminal Not used
183
LOCK
O
GFS is sampled by 460 Hz “H” output when GFS is “H”
184
VSS7
—
Digital ground terminal
185
MD2
I
Digital out on/off control signal input terminal “L”: digital out off, “H”: digital out on
Not used
Not used
186
SCSY
I
Guard subcode sync (S0+S1) resynchronization input terminal Not used
187
PWMI
I
Spindle motor external control signal input terminal Not used
188
VDD8
—
Digital power supply terminal (+2.5V) (for CD-DSP block)
189
XTSL
I
Input terminal for the system clock frequency setting
“L”: 16.9344 MHz, “H”: 33.8688MHz Fixed at “H” in this set
“L”: 16.9344 MHz, “H”: 33.8688MHz Fixed at “H” in this set
190
VSS8
—
Digital ground terminal
191
PVS2
—
Analog ground terminal (for PLL2)
192
LPFI
I
Connected terminal of PLL2 filter
193
LPFO
O
Connected terminal of PLL2 filter
194
PVD2
—
Analog power supply terminal (+2.5V) (for PLL2)
195, 196
NC
—
Not used
197
PVD1
—
Analog power supply terminal (+2.5V) (for PLL1)
198
PVS1
—
Analog ground terminal (for PLL1)
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