Sony CPF-IX001 / NAS-IX001P Service Manual ▷ View online
25
NAS-IX001P
•
IC Pin Function Description
ETHER BOARD IC003 CXD9207GG (ETHERNET/AUDIO CONTROLLER)
Pin No.
Pin Name
I/O
Description
A1
VSS
-
Ground terminal
A2 to A4
PAD[29],
PAD[27], PAD[28]
I/O
Two-way address and data bus with the wireless LAN module
A5
XCBE[3]
I/O
Bus command and byte enable signal input/output with the wireless LAN module
A6 to A9
PAD[23], PAD[22],
PAD[20], PAD[17]
I/O
Two-way address and data bus with the wireless LAN module
A10
XCBE[2]
I/O
Bus command and byte enable signal input/output with the wireless LAN module
A11
XIRDY
I/O
Initiator ready signal input/output with the wireless LAN module
A12
XTRDY
I/O
Target ready signal input/output with the wireless LAN module
A13
XDEVSEL
I/O
Device select signal input/output with the wireless LAN module
A14 to
A17
PAD[14], PAD[13],
PAD[11], PAD[9]
I/O
Two-way address and data bus with the wireless LAN module
A18
XCBE[0]
I/O
Bus command and byte enable signal input/output with the wireless LAN module
A19, A20 PAD[6], PAD[5]
I/O
Two-way address and data bus with the wireless LAN module
A21
VDDE
-
Power supply terminal (+3.3V)
A22
VSS
-
Ground terminal
B1
XGNT[0]
I/O
Host mode: Bus grant signal output to the wireless LAN module
Device mode: Bridge grant signal input from the wireless LAN module
Device mode: Bridge grant signal input from the wireless LAN module
B2 to B8
PAD[31], PAD[30],
PAD[25], PAD[26],
PAD[24], PAD[21],
PAD[25], PAD[26],
PAD[24], PAD[21],
PAD[19]
I/O
Two-way address and data bus with the wireless LAN module
B9
PAR
I/O
Parity signal input/output with the wireless LAN module
B10, B11
PAD[18], PAD[16]
I/O
Two-way address and data bus with the wireless LAN module
B12
XFRAME
I/O
Frame signal input/output with the wireless LAN module
B13
XSTOP
I/O
Stop signal input/output with the wireless LAN module
B14
XCBE[1]
I/O
Bus command and byte enable signal input/output with the wireless LAN module
B15 to
B19
PAD[15], PAD[12],
PAD[10], PAD[8],
PAD[7]
I/O
Two-way address and data bus with the wireless LAN module
B20
VDDI
-
Power supply terminal (+1.2V)
B21, B22 PAD[4], PAD[2]
I/O
Two-way address and data bus with the wireless LAN module
C1
XREQ[0]
I/O
Host mode: Bus request signal input from the wireless LAN module
Device mode: Bridge request signal output to the wireless LAN module
Device mode: Bridge request signal output to the wireless LAN module
C2 to C5
VDDE
-
Power supply terminal (+3.3V)
C6
XPRST
I/O
Reset signal input/output with the wireless LAN module
C7
XINTA
I/O
Host mode: Interrupt signal input from the wireless LAN module
Device mode: Bridge interrupt signal output to the wireless LAN module
Device mode: Bridge interrupt signal output to the wireless LAN module
C8
XINTB
I/O
Host mode: Interrupt signal input from the wireless LAN module
Device mode: OHCI interrupt signal output to the wireless LAN module
Device mode: OHCI interrupt signal output to the wireless LAN module
C9
XREQ[1]
I/O
Host mode: Bus request signal input from the wireless LAN module
Device mode: OHCI request signal output to the wireless LAN module
Not used
Device mode: OHCI request signal output to the wireless LAN module
Not used
C10
XGNT[1]
I/O
Host mode: Bus grant signal output to the wireless LAN module
Device mode: OHCI grant signal input from the wireless LAN module
Not used
Device mode: OHCI grant signal input from the wireless LAN module
Not used
C11
XSERR
I/O
System error signal input/output with the wireless LAN module
C12
XPERR
I/O
Parity error signal input/output with the wireless LAN module
26
NAS-IX001P
Pin No.
Pin Name
I/O
Description
C13
IDSEL[0]
I
Bridge ID selection signal input terminal Fixed at "L" in this set
C14
IDSEL[1]
I
OHCI ID selection signal input terminal Fixed at "L" in this set
C15
DEVICEMODE
I
Device mode control signal input terminal Fixed at "L" in this set
C16, C17
VDDI
-
Power supply terminal (+1.2V)
C18
VDDE
-
Power supply terminal (+3.3V)
C19
VSS
-
Ground terminal
C20
VDDE
-
Power supply terminal (+3.3V)
C21, C22 PAD[3], PAD[0]
I/O
Two-way address and data bus with the wireless LAN module
D1
IPCLK
I
Clock signal input from the wireless LAN module
D2
VSS
-
Ground terminal
D3
OPCLK
O
Clock (29.5 MHz) signal output to the wireless LAN module
D4 to D18
VSS
-
Ground terminal
D19
VDDE
-
Power supply terminal (+3.3V)
D20
VSS
-
Ground terminal
D21
VDDE
-
Power supply terminal (+3.3V)
D22
PAD[1]
I/O
Two-way address and data bus with the wireless LAN module
E1
VDDE
-
Power supply terminal (+3.3V)
E2
NSRST
I/O
System reset signal input/output terminal (for JTAG) Not used
E3
TDO
O
Data output terminal (for JTAG) Not used
E4
RTCK
O
Return clock signal output terminal (for JTAG) Not used
E5, E6
VDDI
-
Power supply terminal (+1.2V)
E7 to E17
VDDE
-
Power supply terminal (+3.3V)
E18
VDDI
-
Power supply terminal (+1.2V)
E19
VSS
-
Ground terminal
E20
USBPW33
-
Power supply terminal (+3.3V) (for USB)
E21
UHDP[1]
I/O
USB data (+) input/output terminal Not used
E22
UHDM[1]
I/O
USB data (-) input/output terminal Not used
F1
TCK
I
Clock signal input terminal (for JTAG) Not used
F2
TMS
I
Mode select signal input terminal (for JTAG) Not used
F3
TDI
I
Data input terminal (for JTAG) Not used
F4
NTRST
I
Test reset signal input terminal (for JTAG) Not used
F5
VDDI
-
Power supply terminal (+1.2V)
F18
USBPW12
-
Power supply terminal (+1.2V) (for USB)
F19
USBGND
-
Ground terminal (for USB)
F20
UHDP[2]
I/O
USB data (+) input/output terminal Not used
F21
UHDM[2]
I/O
USB data (-) input/output terminal Not used
F22
USBCLK
I
USB clock (48 MHz) signal input terminal Not used
G1
PLLVDD
-
Power supply terminal (+1.2V) (for PLL)
G2
PLLVSS
-
Ground terminal (for PLL)
G3
VSS
-
Ground terminal
G4
CPUCLK
I
CPU clock (24.576 MHz) signal input terminal
G5
VDDE
-
Power supply terminal (+3.3V)
G18
VSS
-
Ground terminal
G19
MDIO
I/O
Management data input/output with ethernet interface
G20
MDC
O
Management data clock signal output to the ethernet interface
G21, G22 RXD[3], RXD[2]
I
Receive data input from the ethernet interface
H1
PLLBYPASS
I
PLL bypass mode setting terminal Fixed at "L" in this set
27
NAS-IX001P
Pin No.
Pin Name
I/O
Description
H2
SCANTEST
I
Scan test terminal
H3
REFCLK
I
Reference clock (24.576 MHz) signal output terminal
H4
VPD
I
Test VPD terminal
H5
VSS
-
Ground terminal
H18
VDDE
-
Power supply terminal (+3.3V)
H19, H20 RXD[1], RXD[0]
I
Receive data input from the ethernet interface
H21
RXDV
I
Receive data valid signal input from the ethernet interface
H22
RXERR
I
Receive error signal input from the ethernet interface
J1
X0A
I
Sub system clock signal input terminal (22.5792 MHz)
J2
VSS
-
Ground terminal
J3
X1A
O
Sub system clock signal output terminal (22.5792 MHz)
J4
VSS
-
Ground terminal
J5
VDDI
-
Power supply terminal (+1.2V)
J9 to J14
VSS
-
Ground terminal
J18
VDDI
-
Power supply terminal (+1.2V)
J19
VSS
-
Ground terminal
J20
RXCLK
I
Receive clock signal input from the ethernet interface
J21
VSS
-
Ground terminal
J22
TXCLK
I
Transmit clock signal input from the ethernet interface
K1 to K4
MODE[3] to
MODE[0]
I
Test mode setting terminal Fixed at "L" in this set
K5, K9
to K14
VSS
-
Ground terminal
K18
VDDE
-
Power supply terminal (+3.3V)
K19
TXERR
O
Transmit error signal output to the ethernet interface
K20
TXEN
O
Transmit enable signal output to the ethernet interface
K21, K22 TXD[0], TXD[1]
O
Transmit data output to the ethernet interface
L1
X0
I
Main system clock signal input terminal (24.576 MHz)
L2
VSS
-
Ground terminal
L3
X1
O
Main system clock signal output terminal (24.576 MHz)
L4
VSS
-
Ground terminal
L5
VDDE
-
Power supply terminal (+3.3V)
K9 to
L14, L18
VSS
-
Ground terminal
L19, L20 TXD[2], TXD[3]
O
Transmit data output to the ethernet interface
L21
COL
I
Collision detection signal input from the ethernet interface
L22
CRS
I
Carrier sense signal input from the ethernet interface
M1
XRST
I
Ethernet reset signal input from the display controller "L": reset
M2
VSS
-
Ground terminal
M3
TRCCLK
O
Trace clock signal output terminal Not used
M4
VDDI
-
Power supply terminal (+1.2V)
M5, M9
to M14
VSS
-
Ground terminal
M18
VDDE
-
Power supply terminal (+3.3V)
M19
VSS
-
Ground terminal
M20 to M22 MD[23] to MD[21]
I/O
Two-way data bus terminal Not used
N1 to N4
TRCPKT[7] to
TRCPKT[4]
O
Trace packet signal output terminal Not used
28
NAS-IX001P
Pin No.
Pin Name
I/O
Description
N5
VDDE
-
Power supply terminal (+3.3V)
N9 to N14
VSS
-
Ground terminal
N18
VDDE
-
Power supply terminal (+3.3V)
N19 to N22 MD[20] to MD[17]
I/O
Two-way data bus terminal Not used
P1 to P4
TRCPKT[3] to
TRCPKT[0]
O
Trace packet signal output terminal Not used
P5, P9 to
P14, P18
P14, P18
VSS
-
Ground terminal
P19
VDDI
-
Power supply terminal (+1.2V)
P20
MD[16]
I/O
Two-way data bus terminal Not used
P21
XMBE[2]
O
Data mask signal output terminal Not used
P22
MD[24]
I/O
Two-way data bus terminal Not used
R1
TRCSYNC
O
Trace sync signal output terminal Not used
R2 to R4
PIPESTAT[2] to
PIPESTAT[0]
O
Trace pipestatus signal output terminal Not used
R5, R18
VDDE
-
Power supply terminal (+3.3V)
R19 to R22
MD[25] to MD[28]
I/O
Two-way data bus terminal Not used
T1
VSS
-
Ground terminal
T2
SCL
I/O
Two-way I2C clock bus with the ethernet interface
T3
VDDI
-
Power supply terminal (+1.2V)
T4
SDA
I/O
Two-way I2C data bus with the ethernet interface
T5
VDDE
-
Power supply terminal (+3.3V)
T18
VSS
-
Ground terminal
T19 to T21
MD[29] to MD[31]
I/O
Two-way data bus terminal Not used
T22
XMBE[3]
O
Data mask signal output terminal Not used
U1
BCKI
I
Audio bit clock signal input terminal Not used
U2
VSS
-
Ground terminal
U3
BCKO
O
Audio bit clock signal output to the D/A converter
U4
LRCKO
O
Audio L/R sampling clock signal output to the D/A converter
U5, U18
VDDE
-
Power supply terminal (+3.3V)
U19
VDDI
-
Power supply terminal (+1.2V)
U20 to U22
MD[2] to MD[0]
I/O
Two-way data bus with the SD-RAM and flash ROM
V1
SDOUT
O
Audio serial data output to the D/A converter
V2
FSCLKO
O
Clock signal output to the D/A converter
V3
LRCKI
I
Audio L/R sampling clock signal input terminal Not used
V4
SDINP
I
Audio serial data input terminal Not used
V5
VSS
-
Ground terminal
V6, V7
VDDE
-
Power supply terminal (+3.3V)
V8
VSS
-
Ground terminal
V9
VDDE
-
Power supply terminal (+3.3V)
V10
VSS
-
Ground terminal
V11
VDDE
-
Power supply terminal (+3.3V)
V12
VSS
-
Ground terminal
V13
VDDE
-
Power supply terminal (+3.3V)
V14
VSS
-
Ground terminal
V15
VDDE
-
Power supply terminal (+3.3V)
V16
VSS
-
Ground terminal
V17
VDDE
-
Power supply terminal (+3.3V)
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