Sony CMT-SE5 / CMT-SE9 / HCD-SE5 / HCD-SE9 Service Manual ▷ View online
93
HCD-SE5/SE9
• IC901 CXP973064-237R (MECHANISM CONTROLLER) (DMBSE BOARD)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14 to 21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43, 44
45
46
47
48
49
50
51
52
53
54
55
56
I/O
O
O
O
O
I/O
I
O
O
I
O
O
O
—
I/O
I
I
O
O
I
O
O
I
I
I
O
I
O
O
O
O
I
—
I
O
—
O
O
O
I
I
O
O
O
I
O
O
—
I
Pin Name
NO USE
SDEN
DOCTRL/
ISBTEST
XPST_2753
SDA_EEP
MNT1
FCS_JMP_1
FCS_JMP_2
SENS_CD
CDSP2
CDSP4
XCS_DVD
VSS
D0 to D7
INIT0_DVD
INIT1_DVD
MSCK_SAMBA
XRST_1882
SCOR
LAT_CD
LDON
MIRR
COUT_CD
INLIM
CS_ZIVA
SI_ZIVA
SO_ZIVA
SCK_ZIVA
DRVIRQ
DRVRDY
RST
VSS
XTAL
EXTAL
VDD
SLED A, SLED B
JIT_OFFSET
SDOUT_DSD
SDIN_DSD
READY_DSD
DATA_CD
CLOK_CD
XMSLAT
SQSO
MUTE_DSD
SQCK
VSS
CONTROL_2
Description
Not used
Serial data enable signal output to DVD/CD RF amplifier
Digital out on/off control signal output to the digital signal processor
“L”: digital out off, “H”: digital out on
“L”: digital out off, “H”: digital out on
Reset signal output for DSD decoder
Two-way data bus with the EEPROM
EEPROM ready signal input from the DVD decoder
Focus jump 1 signal output to the motor/coil driver
Focus jump 2 signal output to the motor/coil driver
Internal status (SENSE) signal input from the digital signal processor
CD double speed signal output
CD four times speed signal output (not used)
Chip select signal output to the DVD decoder
Ground terminal (digital system)
Two-way data bus with the DVD decoder
Interrupt signal input from the DVD decoder
Interrupt signal input from the DVD decoder
Serial data transfer clock signal output to the DSD decoder
Reset signal output to the DVD decoder “L”: reset
Subcode sync (S0+S1) detection signal input from the digital signal processor
Serial data latch pulse signal output to the digital signal processor
Laser diode on/off control signal output to the DVD/CD RF amplifier
“L”: laser diode off, “H”: laser diode on
“L”: laser diode off, “H”: laser diode on
Mirror signal input from the digital signal processor
Numbers of track counted signal input from the digital signal processor
Detection signal input from limit in switch The optical pick-up is in the innermost position when “H”
Chip select signal output to the DVD system processor
Serial data input from the DVD system processor
Serial data output to the DVD system processor
Serial data transfer clock signal output to the DVD system processor
Interrupt request signal output to the DVD system processor
Ready signal output to the DVD system processor
System reset signal input from the DVD system processor “L”: reset
Ground terminal (digital system)
System clock input terminal (20 MHz)
System clock output terminal (20 MHz)
Power supply terminal (+3.3V) (digital system)
Sled motor drive signal output
Output terminal for offset adjustment of APEO
Serial data output to the DSD decoder
Serial data input from the DSD decoder
Ready signal input from the DSD decoder “L”: ready
Serial data output to the digital signal processor
Serial data transfer clock signal output to the digital signal processor
Serial data latch pulse signal output to the DSD decoder
Subcode Q data input from the digital signal processor
Muting on/off control signal output to the DSD decoder “H”: muting on
Subcode Q data reading clock signal output to the digital signal processor
Ground terminal (digital system)
Not used
94
HCD-SE5/SE9
Pin No.
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89 to 96
97
98
99
100
Pin Name
CONTROL_1
GFS_DVD
MUTE_CD
MUTE_2D
SLED
FG
SP_ON
JIT
TE
PI
FE
AVSS
AVREF
AVDD
GFS_CD
SCLK_CD
TSD-M
FOK_CD
LOCK_CD
LDSEL
SACD/DVD
I2C_SIO
I2C_SCL
RXD
TXD
SDCLK_RF
SDATA_RF
XWR
XRD
(PWE)
VDD
VSS
A0 to A7
DSAVE
XDRST
WP_EEP
SCL_EEP
I/O
I
I
O
O
I
I
O
I
I
I
I
—
I
—
I
O
O
I
I
O
O
I/O
I/O
I
O
O
I/O
O
O
—
—
—
O
O
O
O
O
Description
Not used
Guard frame sync signal input from the DVD decoder
Muting on/off control signal output to the digital signal processor “H”: muting on
Muting on/off control signal output to the motor/coil driver “H”: muting on
Sled motor servo drive PWM signal input terminal
Spindle motor control signal input
Muting on/off control signal output to the motor/coil driver “H”: muting on
Jitter signal input
Tracking error signal input from the DVD/CD RF amplifier
Pull in signal input from the DVD/CD RF amplifier
Focus error signal input from the DVD/CD RF amplifier
Ground terminal (for A/D converter)
Reference voltage input terminal (for A/D converter)
Power supply terminal (+3.3V) (for A/D converter)
Guard frame sync signal input from the digital signal processor
SENSE serial data reading clock signal output to the digital signal processor
Thermal shut down signal output to the motor/coil driver
Focus OK signal input from the digital signal processor
GFS is sampled by 460 Hz “H” input when GFS is “H”
Laser diode selection signal output
“SACD/DVD selection signal output “L”: DVD, “H”: SACD”
Communication data bus with the DVD system processor and system controller
Communication data reading clock signal input or transfer clock signal output with the DVD system processor
and system controller
and system controller
Serial data input (RS-232C)
Serial data output (RS-232C)
Serial data transfer clock signal output to the DVD/CD RF amplifier
Two-way data bus with the DVD/CD RF amplifier
Write strobe signal output to the DVD decoder
Read strobe signal output to the DVD decoder
Not used
Power supply terminal (+3.3V) (digital system)
Ground terminal (digital system)
Address signal output to the DVD decoder
Motor/coil driver power save control signal output terminal
Reset signal output to the digital signal processor and DSD decoder “L”: reset
Write protect signal output to the EEPROM
Clock signal output to the EEPROM
95
HCD-SE5/SE9
• IC1601 CXD9689AR (DIGITAL AUDIO SIGNAL PROCESSOR) (DMBSE BOARD)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23 to 25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
I/O
—
I
I
I
—
I
O
—
—
—
—
—
I
O
I
—
I
I
O
O
—
I/O
O
O
O
I
I
I
—
O
I
I
O
I
O
O
O
—
—
O
O
O
O
—
I
—
I
O
—
O
Pin Name
VSS
XRST
EXTIN
FS2
VDD1
FS1
PLOCK
VSS
MCLK1
VDDI
VSS
MCLK2
MS
SCKOUT
LRCKI1
VDDE
BCKI1
SDI1
LRCKO
BCKO
VSS
KFSIO
SDO1 to SDO3
SDO4
SPDIF
LRCKI2
BCKI2
SDI2
VSS
HACN
HDIN
HCLK
HDOUT
HCS
SDCLK
CLKEN
RAS
VDDI
VSS
CAS
DQM/OE0
CS0
WE0
VDDE
WMD1
VSS
WMD0
PAGE2
VSS
PAGE1
Description
Ground terminal
Rest input from the system controller
Not used (connected to the ground)
Not used (connected to the ground)
Power supply terminal (+2.5V)
Not used (connected to the ground)
Internal PLL lock signal output (not used (open))
Ground terminal
Resonator terminal (13.5MHz)
Power supply terminal (+2.5V)
Ground terminal
Resonator terminal (13.5MHz)
Master/slave operation selection terminal (L : internal clock) (fixed at “L”)
Internal system clock output to the D/A converter (IC332)
Sampling clock input from the IC802
Power supply terminal (+3.3V)
Bit clock input from the IC802
Data input from the IC802
Sampling clock output to the D/A converter (IC332)
Bit clock output to the D/A converter (IC332)
Ground terminal
Audio clock (384fs/256fs) input from the IC802
Serial data output to the stream processors
Serial data output to the D/A converter (IC332)
SPDIF signal output terminal (not used (open))
Sampling clock input from the A/D converter (IC352)
Bit clock input from the A/D converter (IC352)
Data input from the IC802
Ground terminal
Acknowledge signal output to the system controller (IC501)
Serial data input from the system controller (IC501)
Clock input from the system controller (IC501)
Serial data output to the system controller (IC501)
Chip select signal input from the system controller (IC501)
SDRAM clock (not used (open))
SDRAM clock enable (not used (open))
Row address strobing (not used (open))
Power supply terminal (+2.5V)
Ground terminal
Column address strobing (not used (open))
Data I/O mask (not used (open))
Chip select signal output to the SRAM (IC1602)
Write enable signal output to the SRAM (IC1602)
Power supply terminal (+3.3V)
Setting WAIT mode for external memory (pull up)
Ground terminal
Setting WAIT mode for external memory (pull up)
External memory page switch signal output (not used (open))
Ground terminal
External memory page switch signal output (not used (open))
96
HCD-SE5/SE9
Pin No.
53
54
55
56
57
58
59
60
61
62
63
64 to 66
67
68
69
70
71
72 to 75
76
77 to 80
81
82 to 85
86
87
88
89
90
91
92 to 97
98,99
100
101
102 to 105
106
107,108
109,110
111
112
113
114
115
116
117 to 119
120
Pin Name
PAGE0
BOOT
BTACT
BST
MOD1
MOD0
EXLOCK
VDDI
VSS
A17
A16
A15 to A13
GP10
GP9
GP8
VDDI
VSS
D15/GP7 to D12/GP4
VDDE
D11/GP3 to D8/GP0
VSS
A9 to A10
TDO
TMS
XTRST
TCK
TDI
VSS
A8 to A3
D7,D6
VDDI
VSS
D5 to D2
VDDE
D1,D0
A2,A1
VSS
A0
PM
SD13
SD14
SYNC
VSS
VDDI
I/O
O
I
O
I
I
I
I
—
—
O
O
O
O
O
I
—
—
I/O
—
I/O
—
O
O
I
I
I
I
—
O
I/O
—
—
I/O
—
I/O
O
—
O
I
I
I
I
—
—
Description
External memory page switch signal output (not used (open))
Not used (connected to the ground)
Boot mode status display signal (not used (open))
Boot strap signal input from the system controller (IC501)
Setting for 256fs (PLLx9) (pull up)
Setting for single chip mode (pull down)
Lock signal input terminal
Power supply terminal (+2.5V)
Ground terminal
External memory address (not used (open))
External memory address (not used (open))
Address signal output to the SRAM (IC1602)
LRCK0 signal output
GP9 (ERROR) signal output to the system controller (IC501)
GP8 (AUDIO) signal input from the DIR (IC1371)
Power supply terminal (+2.5V)
Ground terminal
Data input/output from/to the SRAM (IC1602)
Power supply terminal (+3.3V)
Data input/output from/to the SRAM (IC1602)
Ground terminal
Address signal output to the SRAM (IC1602)
Simple emulation data output (not used (open))
Simple emulation data entry beginning and the end terminal (not used (open))
Asynchronous simple BREAK input terminal of emulation (not used (open))
Simple emulation clock input (not used (open))
Simple emulation data entry (not used (open))
Ground terminal
Address signal output to the SRAM (IC1602)
Data input/output from/to the SRAM (IC1602)
Power supply terminal (+2.5V)
Ground terminal
Data input/output from/to the SRAM (IC1602)
Power supply terminal (+3.3V)
Data input/output from/to the SRAM (IC1602)
Address signal output to the SRAM (IC1602)
Ground terminal
Address signal output to the SRAM (IC1602)
PLL initialization signal input from the system controller (IC501)
Data input from the IC802
Data entry terminal (not used (open))
Synchronization / asynchronous selection terminal (L:Sync. H:Async.) (fixed at “H”)
Ground terminal
Power supply terminal (+2.5V)
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