Sony CMT-SE5 / CMT-SE9 / HCD-SE5 / HCD-SE9 Service Manual ▷ View online
89
HCD-SE5/SE9
Pin No.
128, 129
130
131
132
133, 134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172 to 176
Pin Name
VCCA3, VCCA2
PD0
PDHVCC
FDO
GNDA2, GNDA1
SPO
VC2
MDIN2
MDIN1
VCCA1
CLVS
VSS
MDSOUT
VDD
MDPOUT
DEFECT
GSCOR
EXCK
SBIN
VSS
SCOR
WFCK
VDD5V
XRCI
VDDS
C2PO
VDD
DBCK
BCLK
DDAT
MDAT
VSS
DLRC
LRCK
XRST
IFS0
IFS1
XTAL
VSS
XTL2
XTL1
VDD
D0 to D4
I/O
—
O
I
O
—
O
I
I
I
—
O
—
O
—
O
I
I
O
I
—
I
I
—
I
—
I
—
O
I
O
I
—
O
I
I
I
I
I
—
O
I
—
I/O
Description
Power supply terminal (+3.3V) (analog system)
Signal output from the charge pump for phase comparator
Middle point voltage input terminal for RF PLL
Signal output from the charge pump for frequency comparator
Ground terminal (analog system)
Spindle motor control signal output
Middle point voltage (+1.65V) input terminal
Spindle motor servo drive signal input
MDP input terminal
Power supply terminal (+3.3V) (analog system)
Control signal output for selection of the spindle control filter constant at CLVS
Ground terminal (digital system)
Frequency error output terminal of internal CLV circuit
Power supply terminal (+3.3V) (digital system)
Phase error output terminal of internal CLV circuit
Defect signal input terminal (conected to ground terminal)
Guard subcode sync (S0+S1) detection signal input from the digital signal processor
Subcode serial data reading clock signal output to the digital signal processor
Subcode serial data input from the digital signal processor
Ground terminal (digital system)
Subcode sync (S0+S1) detection signal input from the digital signal processor
Write frame clock signal input from the digital signal processor
Power supply terminal (+5V)
RAM overflow signal input terminal (conected to ground terminal)
Power supply terminal (+5V) (digital system)
C2 pointer signal input from the digital signal processor
Power supply terminal (+3.3V) (digital system)
Bit clock signal (2.8224 MHz) output terminal (not used)
Bit clock signal (2.8224 MHz) input from the digital signal processor
PCM data output terminal (not used)
Serial data input from the digital signal processor
Ground terminal (digital system)
L/R sampling clock signal (44.1 kHz) output terminal (not used)
L/R sampling clock signal (44.1 kHz) input from the digital signal processor
Reset signal input from the mechanism controller “L”: reset
Interface selection signal input terminal Fixed at “L” in this set
Interface selection signal input terminal Fixed at “H” in this set
33.8688 MHz clock signal input terminal
Ground terminal (digital system)
System clock output terminal (33.8688 MHz)
System clock input terminal (33.8688 MHz)
Power supply terminal (+3.3V) (digital system)
Two-way data bus with the mechanism controller
90
HCD-SE5/SE9
• IC801 CXD2753R (DSD DECODER) (DMBSE BOARD)
Pin No.
Pin Name
I/O
Description
1
VSCA0
—
Ground terminal (for core)
2
XMSLAT
I
Serial data latch pulse signal input from the mechanism controller
3
MSCK
I
Serial data transfer clock input from the mechanism controller
4
MSDATI
I
Serial data input from the mechanism controller
5
VDCA0
—
Power supply terminal (+2.5V) (for core)
6
MSDATO
O
Serial data output to the mechanism controller
7
MSREADY
O
Ready signal output to the mechanism controller “L”: ready
8
XMSDOE
O
Serial data output enable signal output terminal (not used)
9
XRST
I
Reset signal input from the mechanism controller “L”: reset
10
SMUTE
I
Soft muting on/off control signal input from the mechanism controller “H”: muting on
11
MCKI
I
Master clock (33.8688 MHz) input
12
VSIOA0
—
Ground terminal (for I/O)
13
EXCKO1
O
Master clock (33.8688 MHz) output to the digital audio processor
14
EXCKO2
O
External clock 2 output terminal (not used)
15
LRCK
O
L/R sampling clock (44.1kHz) output terminal (not used)
16
F75HZ
O
Not used
17
VDIOA0
—
Power supply terminal (+3.3V) (for I/O)
18 to 25
MNT0 to MNT7
O
Monitor signal output terminal (not used)
26
TCK
I
Clock input from the DVD system processor for the test
27
TDI
I
Serial data input from the DVD system processor for the test
28
VSCA1
—
Ground terminal (for core)
29
TDO
O
Serial data output to the DVD system processor for the test
30
TMS
I
TMS signal input from the DVD system processor for the test
31
TRST
I
Reset signal input from the DVD system processor for the test “L”: reset
32 to 34 TEST1 to TEST3
I
Input terminal for the test (normally: fixed at “L”)
35
VDCA1
—
Power supply terminal (+2.5V) (for core)
36
UBIT
O
Not used
37
XBIT
O
Not used
38 to 41
SUPDT0 to
SUPDT3
O
Supplementary data output terminal (not used)
42
VSIOA1
—
Ground terminal (for I/O)
43, 44
SUPDT4, SUPDT5
O
Supplementary data output terminal (not used)
45
VDIOA1
—
Power supply terminal (+3.3V) (for I/O)
46, 47
SUPDT6, SUPDT7
O
Supplementary data output terminal (not used)
48
SUPEN
O
Supplementary data enable signal output terminal (not used)
49
VSCA2
—
Ground terminal (for core)
50
NC
O
Not used
51, 52
TEST4, TEST5
I
Input terminal for the test (normally: fixed at “L”)
53
NC
O
Not used
54
VDCA2
—
Power supply terminal (+2.5V) (for core)
55
DSADML
O
DSD data output for L-ch Down Mix
56
DSADMR
O
DSD data output for R-ch Down Mix
57
BCKASL
I
Input/output selection signal input terminal of bit clock (2.8224 MHz) for DSD data output
“L”: input (slave), “H”: output (master) Fixed at “H” in this set
“L”: input (slave), “H”: output (master) Fixed at “H” in this set
58
VSDSD0
—
Ground terminal (for DSD data output)
59
BCKAI
I
Bit clock (2.8224 MHz) input terminal for DSD data output (not used)
60
BCKAO
O
Bit clock (2.8224 MHz) output terminal for DSD data output
91
HCD-SE5/SE9
Pin No.
Pin Name
I/O
Description
61
PHREFI
I
Bit clock (2.8224 MHz) input terminal for DSD data output (not used)
62
PHREFO
O
Bit clock (2.8224 MHz) output to the digital audio processor (not used)
63
ZDFL
O
Front L-ch Zero data flag detection signal output terminal (not used)
64
DSAL
O
Front L-ch DSD data output to the digital audio processor
65
ZDFR
O
Front R-ch Zero data flag detection signal output terminal (not used)
66
DSAR
O
Front R-ch DSD data output to the digital audio processor
67
VDDSD0
—
Power supply terminal (+3.3V) (for DSD data output)
68
ZDFC
O
Center zero data flag detection signal output terminal (not used)
69
DSAC
O
Center DSD data output to the digital audio processor
70
ZDFLFE
O
Woofer zero data flag detection signal output terminal (not used)
71
DSALFE
O
Woofer DSD data output to the digital audio processor
72
VSDSD1
—
Ground terminal (for DSD data output)
73
ZDFLS
O
Rear L-ch zero data flag detection signal output terminal (not used)
74
DSALS
O
Rear L-ch DSD data output to the digital audio processor
75
ZDFRS
O
Rear R-ch zero data flag detection signal output terminal (not used)
76
DSARS
O
Rear R-ch DSD data output to the digital audio processor
77
VDDSD
—
Power supply terminal (+3.3V) (For DSD data output)
78, 79
IOUT0, IOUT1
O
Data output terminal for IEEE 1394 link chip interface (not used)
80
VSCB0
—
Ground terminal (for core)
81, 82
IOUT2, IOUT3
O
Data output terminal for IEEE 1394 link chip interface (not used)
83
VDCB0
—
Power supply terminal (+2.5V) (for core)
84, 85
IOUT4, IOUT5
O
Data output terminal for IEEE 1394 link chip interface (not used)
86
VSIOB0
—
Ground terminal (for I/O)
87
IANCO
O
Transmission information data output terminal for IEEE 1394 link chip interface (not used)
88
IFULL
I
Data transmission hold request signal input terminal for IEEE 1394 link chip interface (not used)
89
IEMPTY
I
High speed transmission request signal input terminal for IEEE 1394 link chip interface
(not used)
(not used)
90
VDIOB0
—
Power supply terminal (+3.3V) (for I/O)
91
IFRM
O
Frame reference signal output terminal for IEEE 1394 link chip interface (not used)
92
IOUTE
O
Enable signal output terminal for IEEE 1394 link chip interface (not used)
93
IBCK
O
Data transmission clock output terminal for IEEE 1394 link chip interface (not used)
94
VSCB1
—
Ground terminal (for core)
95
IERR
I
Not used
96
IANCI
I
Not used
97
IPLAN
I
Not used
98
IHOLD
O
Not used
99
VDCB1
—
Power supply terminal (+2.5V) (for core)
100
IVLD
I
Not used
101 to 105
Not used
106
VSIOB1
—
Ground terminal (for I/O)
107 to 109
Not used
110
VDIOB1
—
Power supply terminal (+3.3V) (for I/O)
111 to 114 WAD0 to WAD3
I
External A/D data input terminal for PSP physical disc mark detection (not used)
115
TESTI
I
Input terminal for the test (normally: fixed at “L”)
116
VSCB2
—
Ground terminal (for core)
117 to 120 WAD4 to WAD7
I
External A/D data input terminal for PSP physical disc mark detection (not used)
121
VDCB2
—
Power supply terminal (+2.5V) (for core)
IDIN0 to IDIN4
IDIN5 to IDIN7
I
I
92
HCD-SE5/SE9
Pin No.
Pin Name
I/O
Description
122
WRFD
I
Not used
123
WCK
I
Operation clock input for PSP physical disc mark detection from the DVD decoder
124, 125
WAVDD0,
WAVDD1
—
A/D power supply terminal (+2.5V) (for PSP physical disc mark detection)
126
WARFI
I
Analog RF signal input for PSP physical disc mark detection from the DVD/CD RF amplifier
127
WAVRB
I
A/D bottom reference terminal for PSP physical disc mark detection
128, 129
WAVSS0, WAVSS1
—
A/D ground terminal (for PSP physical disc mark detection)
130
VSIO
—
Ground terminal (for I/O)
131 to 134
DQ7 to DQ4
I/O
Two-way data bus with the SD-RAM
135
VDIOA2
—
Power supply terminal (+3.3V) (for I/O)
136 to 139
Two-way data bus with the SD-RAM
140
VSIOA3
—
Ground terminal (for I/O)
141
DCLK
O
Clock output to the SD-RAM
142
DCKE
O
Clock enable signal output to the SD-RAM
143
XWE
O
Write enable signal output to the SD-RAM
144
XCAS
O
Column address strobe signal output to the SD-RAM
145
XRAS
O
Row address strobe signal output to the SD-RAM
146
VDIOA3
—
Power supply terminal (+3.3V) (for I/O)
147
NC
O
Not used
148, 149
A11, A10
O
Address signal output to the SD-RAM
150
VSCA3
—
Ground terminal (for core)
151, 152
A9, A8
O
Address signal output to the SD-RAM
153
VDCA3
—
Power supply terminal (+2.5V) (for core)
154 to 157
Address signal output to the SD-RAM
158
VSIOA4
—
Ground terminal (for I/O)
159 to 162
A3 to A0
O
Address signal output to the SD-RAM
163
VDIOA4
—
Power supply terminal (+3.3V) (for I/O)
164
XSRQ
O
Serial data request signal output to the DVD decoder
165
XSHD
I
Header flag signal input from the DVD decoder
166
SDCK
I
Serial data transfer clock input from the DVD decoder
167
XSAK
I
Serial data effect flag signal input from the DVD decoder
168
SDEF
I
Error flag signal input from the DVD decoder
169 to 176
SD0 to SD7
I
Stream data input from the DVD decoder
DQ3 to DQ0
I/O
A7 to A4
O
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