Sony CMT-F3MD / HCD-F3MD Service Manual ▷ View online
69
– PANEL Board –
IC601
M66004M8FP
IC931
M62016L
IC171
LB1641
1
2
3
4
5
6
7
8
9
10
GND
MOTOR
DRIVE
NOISE
FILTER
CLAMP
FWD.IN
REV.IN
VCC 1
VCC 2
NOISE
FILTER
MOTOR
DRIVE
MOTOR
DRIVE
MOTOR
DRIVE
T.S.D
O.C.P
FWD/REV/STOP
CONTROL LOGIC
1
2
3
4
5
+
–
INTERRUPT SIGNAL
GENERATING BLOCK
RESET SIGNAL
GENERATING BLOCK
+
–
GND
INT
RESET
CD
VCC
COM
COM
INDICATION
CODE
RESISTOR
(8BIT x 16)
DECODER
(35BIT x 16)
DECODER
(35BIT x 16)
CODE/COMMAND
CONTROL
CIRCUIT
INDICATION
CONTROL
RESISTOR
INDICATION
CONTROLLER
DIGITAL
OUTPUT
CIRCUIT
OUTPUT
CIRCUIT
CODE
WRITE
SERIAL
RECEIVE
CIRCUIT
OUTPUT
PORT
(2BIT)
CLOCK
GENERATOR
CIRCUIT
RAM WRITE
CODE SELECT
DIG12
|
DIG15
V
CC
2
SEG0
|
SEG26
V
SS
XIN
XOUT
V
CC
1
RES
DIG11
|
DIG0
CS
CLK
DATA
SEG35
|
SEG27
P1
P0
14
15
16
17
18
19
20
21
22
23
|
31
13
1
|
12
SEGMENT OUTPUT CIRCUIT
59
|
33
60
32
VP
64
|
61
70
Pin No.
Pin Name
I/O
Description
1
I
I
I-V converted RF signal I input from the optical pick-up block detector
2
J
I
I-V converted RF signal J input from the optical pick-up block detector
3
VC
O
Middle point voltage (+1.65V) generation output terminal
4 to 9
A to F
I
Signal input from the optical pick-up detector
10
PD
I
Light amount monitor input from the optical pick-up block laser diode
11
APC
O
Laser amplifier output terminal to the automatic power control circuit
12
APCREF
I
Reference voltage input for setting laser power from the CXD2654R (IC121)
13
GND
—
Ground terminal
14
TEMPI
I
Connected to the temperature sensor
15
TEMPR
O
Output terminal for a temperature sensor reference voltage
16
SWDT
I
Writing serial data input from the CXD2654R (IC121)
17
SCLK
I
Serial data transfer clock signal input from the CXD2654R (IC121)
18
XLAT
I
Serial data latch pulse signal input from the CXD2654R (IC121)
19
XSTBY
I
Standby signal input terminal “L”: standby (fixed at “H” in this set)
20
F0CNT
I
Center frequency control voltage input terminal of internal circuit (BPF22, BPF3T, EQ) input
from the CXD2654R (IC121)
from the CXD2654R (IC121)
21
VREF
O
Reference voltage output terminal Not used (open)
22
EQADJ
I
Center frequency setting terminal for the internal circuit (EQ)
23
3TADJ
I
Center frequency setting terminal for the internal circuit (BPF3T)
24
VCC
—
Power supply terminal (+3.3V)
25
WBLADJ
I
Center frequency setting terminal for the internal circuit (BPF22)
26
TE
O
Tracking error signal output to the CXD2654R (IC121)
27
CSLED
I
Connected to the external capacitor for low-pass filter of the sled error signal
28
SE
O
Sled error signal output to the CXD2654R (IC121)
29
ADFM
O
FM signal output of the ADIP
30
ADIN
I
Receives a ADIP FM signal in AC coupling
31
ADAGC
I
Connected to the external capacitor for ADIP AGC
32
ADFG
O
ADIP duplex signal (22.05 kHz
±
1 kHz) output to the CXD2654R (IC121)
33
AUX
O
Auxiliary signal (I
3
signal/temperature signal) output to the CXD2654R (IC121)
34
FE
O
Focus error signal output to the CXD2654R (IC121)
35
ABCD
O
Light amount signal (ABCD) output to the CXD2654R (IC121)
36
BOTM
O
Light amount signal (RF/ABCD) bottom hold output to the CXD2654R (IC121)
37
PEAK
O
Light amount signal (RF/ABCD) peak hold output to the CXD2654R (IC121)
38
RF
O
Playback EFM RF signal output to the CXD2654R (IC121)
39
RFAGC
I
Connected to the external capacitor for RF auto gain control circuit
40
AGCI
I
Receives a RF signal in AC coupling
41
COMPO
O
User comparator output terminal Not used (open)
42
COMPP
I
User comparator input terminal Not used (fixed at “L”)
43
ADDC
I
Connected to the external capacitor for cutting the low band of the ADIP amplifier
44
OPO
O
User operational amplifier output terminal Not used (open)
45
OPN
I
User operational amplifier inversion input terminal Not used (fixed at “L”)
46
RFO
O
RF signal output terminal
47
MORFI
I
Receives a MO RF signal in AC coupling
48
MORFO
O
MO RF signal output terminal
6-27.
IC PIN FUNCTION DESCRIPTION
• BD (MD) BOARD IC101 CXA2523AR (RF AMP, FOCUS/TRACKING ERROR AMP)
71
Pin No.
Pin Name
I/O
Description
1
MNT0 (FOK)
O
Focus OK signal output to the MD mechanism controller (IC316)
“H” is output when focus is on (“L”: NG)
“H” is output when focus is on (“L”: NG)
2
MNT1 (SHOCK)
O
Track jump detection signal output to the MD mechanism controller (IC316)
3
MNT2 (XBUSY)
O
Busy monitor signal output to the MD mechanism controller (IC316)
4
MNT3 (SLOCK)
O
Spindle servo lock status monitor signal output to the MD mechanism controller (IC316)
5
SWDT
I
Writing serial data signal input from the MD mechanism controller (IC316)
6
SCLK
I (S)
Serial data transfer clock signal input from the MD mechanism controller (IC316)
7
XLAT
I (S)
Serial data latch pulse signal input from the MD mechanism controller (IC316)
8
SRDT
O (3)
Reading serial data signal output to the MD mechanism controller (IC316)
9
SENS
O (3)
Internal status (SENSE) output to the MD mechanism controller (IC316)
10
XRST
I (S)
Reset signal input from the MD mechanism controller (IC316) “L”: reset
11
SQSY
O
Subcode Q sync (SCOR) output to the MD mechanism controller (IC316)
“L” is output every 13.3 msec Almost all, “H” is output
“L” is output every 13.3 msec Almost all, “H” is output
12
DQSY
O
Digital In U-bit CD format subcode Q sync (SCOR) output to the MD mechanism controller
(IC316) “L” is output every 13.3 msec Almost all, “H” is output
(IC316) “L” is output every 13.3 msec Almost all, “H” is output
13
RECP
I
Laser power selection signal input from the MD mechanism controller (IC316)
“L”: playback mode, “H”: recording mode
“L”: playback mode, “H”: recording mode
14
XINT
O
Interrupt status output to the MD mechanism controller (IC316)
15
TX
O
Recording data output enable signal input from the MD mechanism controller (IC316)
Writing data transmission timing input (Also serves as the magnetic head on/off output)
Writing data transmission timing input (Also serves as the magnetic head on/off output)
16
OSCI
I
System clock signal (512Fs=90.3168 MHz) input terminal
17
OSCO
O
System clock signal (512Fs=90.3168 MHz) output terminal Not used (open)
18
XTSL
I
Input terminal for the system clock frequency setting
“L”: 45.1584 MHz, “H”: 22.5792 MHz (fixed at “H” in this set)
“L”: 45.1584 MHz, “H”: 22.5792 MHz (fixed at “H” in this set)
19
DIN0
I
Digital audio signal input terminal when recording mode Not used
20
DIN1
I
Digital audio signal input terminal when recording mode
21
DOUT
O
Digital audio signal output terminal when playback mode
22
DATAI
I
Serial data input terminal Not used (fixed at “L”)
23
LRCKI
I
L/R sampling clock signal (44.1 kHz) input terminal Not used (fixed at “L”)
24
XBCKI
I
Bit clock signal (2.8224 MHz) input terminal Not used (fixed at “L”)
25
ADDT
I
Recording data input from the A/D, D/A converter (IC201)
26
DADT
O
Playback data output to the A/D, D/A converter (IC201)
27
LRCK
O
L/R sampling clock signal (44.1 kHz) output to the A/D, D/A converter (IC201)
28
XBCK
O
Bit clock signal (2.8224 MHz) output to the A/D, D/A converter (IC201)
29
FS256
O
Clock signal (11.2896 MHz) output terminal Not used (open)
30
DVDD
—
Power supply terminal (+3.3V) (digital system)
31 to 34
A03 to A00
O
Address signal output to the D-RAM (IC124)
35
A10
O
Address signal output to the external D-RAM Not used (open)
36 to 40
A04 to A08
O
Address signal output to the D-RAM (IC124)
41
A11
O
Address signal output to the external D-RAM Not used (open)
42
DVSS
—
Ground terminal (digital system)
43
XOE
O
Output enable signal output to the D-RAM (IC124) “L” active
44
XCAS
O
Column address strobe signal output to the D-RAM (IC124) “L” active
* I (S) stands for schmitt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O.
• BD (MD) BOARD IC121 CXD2654R
(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR, EFM/ACIRC ENCODER/DECODER,
SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER)
(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR, EFM/ACIRC ENCODER/DECODER,
SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER)
72
Pin No.
Pin Name
I/O
Description
45
A09
O
Address signal output to the D-RAM (IC124)
46
XRAS
O
Row address strobe signal output to the D-RAM (IC124) “L” active
47
XWE
O
Write enable signal output to the D-RAM (IC124) “L” active
48
D1
I/O
49
D0
I/O
50
D2
I/O
51
D3
I/O
52
MVCI
I (S)
Digital in PLL oscillation input from the external VCO Not used (fixed at “L”)
53
ASYO
O
Playback EFM full-swing output terminal
54
ASYI
I (A)
Playback EFM asymmetry comparator voltage input terminal
55
AVDD
—
Power supply terminal (+3.3V) (analog system)
56
BIAS
I (A)
Playback EFM asymmetry circuit constant current input terminal
57
RFI
I (A)
Playback EFM RF signal input from the CXA2523AR (IC101)
58
AVSS
—
Ground terminal (analog system)
59
PCO
O (3)
Phase comparison output for master clock of the recording/playback EFM master PLL
60
FILI
I (A)
Filter input for master clock of the recording/playback master PLL
61
FILO
O (A)
Filter output for master clock of the recording/playback master PLL
62
CLTV
I (A)
Internal VCO control voltage input of the recording/playback master PLL
63
PEAK
I (A)
Light amount signal (RF/ABCD) peak hold input from the CXA2523AR (IC101)
64
BOTM
I (A)
Light amount signal (RF/ABCD) bottom hold input from the CXA2523AR (IC101)
65
ABCD
I (A)
Light amount signal (ABCD) input from the CXA2523AR (IC101)
66
FE
I (A)
Focus error signal input from the CXA2523AR (IC101)
67
AUX1
I (A)
Auxiliary signal (I
3
signal/temperature signal) input from the CXA2523AR (IC101)
68
VC
I (A)
Middle point voltage (+1.65V) input from the CXA2523AR (IC101)
69
ADIO
O (A)
Monitor output of the A/D converter input signal Not used (open)
70
AVDD
—
Power supply terminal (+3.3V) (analog system)
71
ADRT
I (A)
A/D converter operational range upper limit voltage input terminal (fixed at “H” in this set)
72
ADRB
I (A)
A/D converter operational range lower limit voltage input terminal (fixed at “L” in this set)
73
AVSS
—
Ground terminal (analog system)
74
SE
I (A)
Sled error signal input from the CXA2523AR (IC101)
75
TE
I (A)
Tracking error signal input from the CXA2523AR (IC101)
76
DCHG
I (A)
Connected to the +3.3V power supply
77
TEST4
I
Input terminal for the test Not used (fixed at “H”)
78
ADFG
I (S)
ADIP duplex FM signal (22.05 kHz
±
1 kHz) input from the CXA2523AR (IC101)
79
F0CNT
O
Filter f0 control signal output to the CXA2523AR (IC101)
80
XLRF
O
Serial data latch pulse signal output to the CXA2523AR (IC101)
81
CKRF
O
Serial data transfer clock signal output to the CXA2523AR (IC101)
82
DTRF
O
Writing serial data output to the CXA2523AR (IC101)
83
APCREF
O
Control signal output to the reference voltage generator circuit for the laser automatic power
control
control
84
TEST0
O
Input terminal for the test Not used (open)
85
TRDR
O
Tracking servo drive PWM signal (–) output to the BH6511FS (IC152)
86
TFDR
O
Tracking servo drive PWM signal (+) output to the BH6511FS (IC152)
87
DVDD
—
Power supply terminal (+3.3V) (digital system)
88
FFDR
O
Focus servo drive PWM signal (+) output to the BH6511FS (IC152)
* I (S) stands for schmitt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O.
Two-way data bus with the D-RAM (IC124)
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