Sony CMT-DH30 / HCD-DH30 Service Manual ▷ View online
HCD-DH30
53
- JACK Board -
IC702 M65850FP-E1
OSCILLATOR
1/2 VCC
AUTO
RESET
LPF1
MAIN
CONTROL
A/D
20KBIT
SRAM
LPF2
D/A
2
3
4
5
6
7
8
9
10
11
15
14
13
12
CLOCK
RESET
MO
MI
D1
DO0
DO1
VCC
16
NC
CLOCK
REF
OP2IN
OP2OUT
LPF2IN
LPF2OUT
LPF1IN
1
NC
LPF1OUT
OP1OUT
OP1IN
CC1
CC2
GND
SEGMENT
DRIVER
GRID
DRIVER
CG-RAM
ADDRESS SELECTOR
DC-RAM
CG-ROM
8 BIT
SHIFT
REGISTER
TIMING
GENERATOR 2
TIMING
GENERATOR 1
COMMAND
DECODER
CONTROL
CIRCUIT
PORT
DRIVER
WRITE
ADDRESS
COUNTER
READ
ADDRESS
COUNTER
GR1
32
SG20
16
SG19
15
GR2
33
OSCI 50
VSS 49
VDD 56
RSTB 52
OSCO 51
AD-RAM
DUTY CONTROL
OSCILLATOR
DIGIT CONTROL
CLKB 54
DIN 55
CSB 53
P1 57
P2 58
P2 58
AD
DRIVER
AD2 59
AD1 60
AD1 60
SG4 64
SG3 63
SG2 62
SG1 61
SG35
31
SG34
30
SG33
29
SG32
28
SG31
27
SG30
26
SG29
25
SG28
24
SG27
23
SG26
22
SG25
21
SG24
20
SG23
19
SG22
18
SG21
17
SG18
14
SG17
13
SG16
12
SG15
11
SG14
10
SG13
9
SG12
8
SG1
1
7
SG10
6
SG9
5
SG8
4
SG7
3
SG6
2
SG5
1
GR3
34
GR4
35
GR5
36
GR6
37
GR7
38
GR8
39
GR9
40
GR10
41
GR1
1
42
GR12
43
GR13
44
GR14
45
GR15
46
GR16
47
VEE
48
- PANEL Board -
IC902 PT6302LQ-010
HCD-DH30
54
CONSTANT
CURRENT
SOURCE
2
FB
1
VDD
4
VCC
5 DRAIN
8 SOURCE
7 SOURCE
7 SOURCE
3
CL
VCL
CLAMP CIRCUIT
(ILIMIT SETTING)
IN
ICL.LOW
VCL.OUT
ILIMIT VARIABLE
CIRCUIT
+
–
–
+
–
+
–
–
7.2V
+
–
–
2.4V
VCC UV
VCC OVP
OVERHEAT
PROTECTION
S
R
R
Q
Q
Q
RESTARTING
TRIGGER
R
S
S
Q
Q
Q
+
–
–
27%
22%
22%
FOR LIGHT LOAD
DETECTION INTERMITTENT
OSCILLATION CONTROL
GENERATOR
CLOCK
12kHz
MAXDC
5.7V
5.0V
5.0V
VDD UV
5.7V
REGULATOR
VDD CLAMP
CIRCUIT
6.6V
+
–
ILIMIT
CORRECTION
CIRCUIT
FOR
DRAIN CURRENT
DETECT
GATE DRIVER
POWER
MOSFET
AT TURNING ON
BLANKING PULSE
GENERATION CIRCUIT
- POWER Board -
IC601 MIP2F20MS1SO
HCD-DH30
55
• IC Pin Function Description
DMB15 BOARD IC102 CXD9849R (RF AMP, SERVO DSP, MPEG DECODER)
Pin No.
Pin Name
I/O
Description
1
AGND
-
Ground terminal
2
DVDA
I
AC coupled input path A
3
DVDB
I
AC coupled input path B
4
DVDC
I
AC coupled input path C
5
DVDD
I
AC coupled input path D
6
DVDRFIP
I
AC coupled DVD RF signal input from the optical pick-up block
7
DVDRFIN
I
AC coupled DVD RF signal input terminal Not used
8
MA
I
DC coupled main-beam RF signal input A
9
MB
I
DC coupled main-beam RF signal input B
10
MC
I
DC coupled main-beam RF signal input C
11
MD
I
DC coupled main-beam RF signal input D
12
SA
I
DC coupled sub-beam RF signal input A Not used
13
SB
I
DC coupled sub-beam RF signal input B Not used
14
SC
I
DC coupled sub-beam RF signal input C Not used
15
SD
I
DC coupled sub-beam RF signal input D Not used
16
CDFON
I
CD focusing error negative input terminal Not used
17
CDFOP
I
CD focusing error positive input terminal Not used
18
TNI
I
3 beam satellite PD signal negative input from the optical pick-up block
19
TPI
I
3 beam satellite PD signal positive input from the optical pick-up block
20, 21
MDI1, MDI2
I
Laser power monitor input from the optical pick-up block
22
LDO2
O
Laser diode drive signal output to the optical pick-up block (for DVD)
23
LDO1
O
Laser diode drive signal output to the optical pick-up block (for CD)
24
SVDD3
-
Power supply terminal (+3.3V)
25
CSO
O
Central servo signal output terminal Not used
26
RFLVL
O
RFRP low pass output terminal Not used
27
SGND
-
Ground terminal
28
V2REFO
O
Reference voltage (+2.8V) output terminal Not used
29
V2O
O
Reference voltage (+2V) output to the optical pick-up block
30
VREFO
O
Reference voltage (+1.4V) output terminal
31
FEO
O
Focus error monitor output terminal Not used
32
TEO
O
Tracking error monitor output terminal Not used
33
TEZISLV
O
Slice level of tracking error signal output terminal Not used
34
OPOUT
O
Output from the internal operational amplifi er Not used
35, 36
OPIN
I
Input to the internal operational amplifi er Not used
37
DMO
O
Spindle motor control signal output to the motor driver
38
FMO
O
Sled motor control signal output to the motor driver
39
TROPENPWM
O
Loading motor control signal output to the motor driver
40
IOPMON
I
Power monitor terminal
41
TRO
O
Tracking coil control signal output to the coil driver
42
FOO
O
Focus coil control signal output to the coil driver
43
DVSS
-
Ground terminal
44, 45
NC
-
Not used
46
DVDD3
-
Power supply terminal (+3.3V)
47
SPFG
I
Spindle motor hall sensor input from the motor driver
48
DSEL
O
Interlace/progressive selection signal output to the video amplifi er
"L": progressive, "H": interlace
"L": progressive, "H": interlace
49
WIDE
O
Normal/squeeze selection signal output to the video amplifi er "L": normal, "H": squeeze
50
MSW
O
CD/DVD selection signal output terminal "L": CD, "H": DVD
51
MAMUTE
O
Muting control signal output terminal Not used
52
DVDD18
-
Power supply terminal (+1.8V)
53 to 61
IOA2 to IOA8,
IOA18, IOA19
IOA18, IOA19
O
Address signal output to the fl ash ROM
62
DVSS
-
Ground terminal
63
APLLCAP
-
Connection terminal for an external capacitor
HCD-DH30
56
Pin No.
Pin Name
I/O
Description
64
APLLVSS
-
Ground terminal
65
VDD3
-
Power supply terminal (+3.3V)
66
IOWR
O
Write enable signal output to the fl ash ROM
67 to 72
IOA16 to IOA11
O
Address signal output to the fl ash ROM
73
DVDD3
-
Power supply terminal (+3.3V)
74 to 76
IOA10, IOA9, IOA20
O
Address signal output to the fl ash ROM
77
IOCS
O
Chip select signal output to the fl ash ROM
78
IOA1
O
Address signal output to the fl ash ROM
79
IOOE
O
Output enable signal output to the fl ash ROM
80
DVDD3
-
Power supply terminal (+3.3V)
81 to 84
AD0 to AD3
I/O
Data/address signal input/output terminal with the fl ash ROM
85
DVSS
-
Ground terminal
86 to 88
AD4 to AD6
I/O
Data/address signal input/output terminal with the fl ash ROM
89
IOA21
O
Address signal output to the fl ash ROM
90
ALE
O
Address latch enable signal output terminal Not used
91
AD7
I/O
Data/address signal input/output terminal with the fl ash ROM
92, 93
IOA17, IOA0
O
Address signal output to the fl ash ROM
94
DVSS
-
Ground terminal
95
UWR
O
Write enable signal output terminal Not used
96
URD
O
Data read enable signal output terminal Not used
97
DVDD18
-
Power supply terminal (+1.8V)
98
IFSDO
O
Serial data output to the system controller
99
IFCK
O
Serial data transfer clock signal output to the system controller
100
XIFCS
O
Chip select signal output to the system controller
101
IFSDI
I
Serial data input from the system controller
102
SCL
O
Serial data transfer clock signal output to the EEPROM and D/A converter
103
SDA
I/O
Two-way data bus with the EEPROM and D/A converter
104
TRG-SW
I
Trigger detection switch input terminal
105
IFBSY
I
Busy signal input from the system controller
106
RXD
I
Receive data input terminal for UART communication when data writing to fl ash memory
107
TXD
O
Transmit data output terminal for UART communication when data writing to fl ash memory
108
DVDD3
-
Power supply terminal (+3.3V)
109
ICE
I
ICE mode enable signal input terminal Not used
110
PRST
I
Reset signal input from the system controller "L": reset
111
IR
I
IR control signal input terminal Not used
112
INT0
O
Interrupt request signal output terminal Not used
113
DQM0
O
Data mask signal output to the SD-RAM
114
MREQ
O
Muting request signal output terminal Not used
115
RD7
I/O
Two-way data bus with the SD-RAM
116
DVSS
-
Ground terminal
117, 118
RD6, RD5
I/O
Two-way data bus with the SD-RAM
119
DVSS
-
Ground terminal
120, 121
RD4, RD3
I/O
Two-way data bus with the SD-RAM
122
DVDD18
-
Power supply terminal (+1.8V)
123 to 126
RD2 to RD0, RD15
I/O
Two-way data bus with the SD-RAM
127
DVDD3
-
Power supply terminal (+3.3V)
128 to 133
RD14 to RD9
I/O
Two-way data bus with the SD-RAM
134
DVSS
-
Ground terminal
135
RD8
I/O
Two-way data bus with the SD-RAM
136
GPIO
-
Not used
137
DQM1
O
Data mask signal output to the SD-RAM
138
RWE
O
Write enable signal output to the SD-RAM
139
CAS
O
Column address strobe signal output to the SD-RAM
140
RAS
O
Row address strobe signal output to the SD-RAM
141
DVDD3
-
Power supply terminal (+3.3V)
142
RCS
O
Chip select signal output to the SD-RAM
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