Sony CMT-DH30 / HCD-DH30 Service Manual ▷ View online
HCD-DH30
57
Pin No.
Pin Name
I/O
Description
143
BA0
O
Bank address signal output to the SD-RAM
144
DVSS
-
Ground terminal
145
BA1
O
Bank address signal output to the SD-RAM
146, 147
RA10, RA0
O
Address signal output to the SD-RAM
148
DVSS
-
Ground terminal
149 to 151
RA1 to RA3
O
Address signal output to the SD-RAM
152
DVDD18
-
Power supply terminal (+1.8V)
153, 154
NC
-
Not used
155
DVDD3
-
Power supply terminal (+3.3V)
156
RCLK
O
Serial data transfer clock signal output to the SD-RAM
157
CKE
O
Clock enable signal output to the SD-RAM
158 to 160
RA11, RA9, RA8
O
Address signal output to the SD-RAM
161
DVSS
-
Ground terminal
162
RA7
O
Address signal output to the SD-RAM
163
DVSS
-
Ground terminal
164 to 166
RA6 to RA4
O
Address signal output to the SD-RAM
167
DVDD3
-
Power supply terminal (+3.3V)
168
DISC/X
-
Not used
169
RGB
-
Not used
170
TSD_M
O
Thermal shut down signal output to the motor/coil driver
171, 172
NC
-
Not used
173
DVDD18
-
Power supply terminal (+1.8V)
174
FWD
O
Loading motor drive signal output to the motor driver (forward direction)
175
NC
-
Not used
176
LIMSW
I
Limit detection switch input terminal
177
OCSW
I
Disc in/out detection switch input terminal
178
REV
O
Loading motor drive signal output to the motor driver (reverse direction)
179
CKSW
I
Chucking detection switch input terminal
180, 181
NC
-
Not used
182
DVDD3
-
Power supply terminal (+3.3V)
183 to 188
NC
-
Not used
189
DAVCC
-
Power supply terminal (+3.3V)
190
VREF
-
For bandgap reference voltage terminal Not used
191
FS
-
Full scale adjustment terminal
192
YUV0
O
Video data output terminal Not used
193
DAVSS
-
Ground terminal
194
YUV1
O
Y signal output to the video amplifi er
195
DAVDD
-
Power supply terminal (+3.3V)
196
YUV2
O
Chroma signal output to the video amplifi er
197
DAVSS
-
Ground terminal
198
YUV3
O
Video signal output to the video amplifi er
199
DAVDD
-
Power supply terminal (+3.3V)
200
YUV4
O
Y signal output to the video amplifi er
201
DAVSS
-
Ground terminal
202, 203
YUV5, YUV6
O
Component video signal output to the video amplifi er
204
DVDD3
-
Power supply terminal (+3.3V)
205
MIC
I
Microphone signal input detection signal input from the system controller
"H": microphone signal input
"H": microphone signal input
206
VOICE
I
Voice signal input terminal (except AEP model)
207
KRMOD
O
Karaoke mode selection signal output to the system controller "H": karaoke mode
208
SMSCK
I
Score signal input terminal (except AEP model)
209
SPDATA
I
SPDIF digital audio data input terminal Not used
210
MUTE
O
Muting signal output to the motor/coil driver
211
MUTE123
O
Muting signal output to the motor/coil driver
212
DVDD3
-
Power supply terminal (+3.3V)
213
ALRCK
O
L/R sampling clock signal output to the D/A converter
HCD-DH30
58
Pin No.
Pin Name
I/O
Description
214
ABCK
O
Bit clock signal output to the D/A converter
215
ACLK
O
Master clock signal output to the D/A converter
216
DVSS
-
Ground terminal
217 to 219 ASDATA1 to ASDATA2
O
Audio serial data output to the D/A converter
220
XRST
O
Reset signal output to the D/A converter "L": reset
221
DVDD18
-
Power supply terminal (+1.8V)
222
ASDATA4
O
Audio serial data output to the D/A converter
223
DVSS
-
Ground terminal
224
DWIDE
-
Not used
225
SPDIF
O
SPDIF digital audio signal output to the digital optical transceiver
226
RFGND18
-
Ground terminal
227
RFVDD18
-
Power supply terminal (+1.8V)
228
XTALO
O
System clock output terminal (27 MHz)
229
XTALI
I
System clock input terminal (27 MHz)
230
JITFO
O
Output terminal of the RF jitter meter
231
JITFN
I
Input terminal of the RF jitter meter
232
PLLVSS
-
Ground terminal
233
IDAC
-
Not used
234
PLLVDD3
-
Power supply terminal (+3.3V)
235
LPFON
O
Data PLL loop fi lter output terminal
236
LPFIP
I
Data PLL loop fi lter input terminal
237
LPFIN
I
Data PLL loop fi lter input terminal
238
LPFOP
O
Data PLL loop fi lter output terminal
239
VDD3
-
Power supply terminal (+3.3V)
240
NC
-
Not used
241
VSS
-
Ground terminal
242, 243
NC
-
Not used
244
RFVDD3
-
Power supply terminal (+3.3V)
245
RFRPDC
O
RF ripple detect output terminal
246
RFRPAC
I
RF ripple detect input terminal
247
HRFZC
I
High frequency RF ripple zero crossing terminal
248
CRTPLP
O
Defect level fi lter capacitor connecting terminal
249
RFGND
-
Ground terminal
250, 251
NC
-
Not used
252
OSP
O
RF offset cancellation capacitor connecting terminal
253
OSN
O
RF offset cancellation capacitor connecting terminal
254
RFGC
O
RF AGC loop capacitor connecting for DVD-ROM
255
IREF
I
Reference current input terminal
256
AVDD3
-
Power supply terminal (+3.3V)
HCD-DH30
59
USB BOARD IC901 TMP92CD28AFG-6UJ5 (USB CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
/RESET
I
Reset signal input from the system controller "L": reset
2
DI
I
Ready to send signal input from the system controller
3, 4
NO USE
O
Not used
5
G-3
I
Function selection signal input terminal Fixed at "L" in this set
6
DVCC
-
Power supply terminal (+3.3 V)
7 to 9
NO USE
O
Not used
10
DVSS
-
Ground terminal
11
DVCC
-
Power supply terminal (+3.3 V)
12
RVOUT1
O
Reference voltage (+3.3 V) output terminal
13, 14
RVIN
I
Reference voltage (+3.3 V) input terminal
15
RVOUT2
O
Reference voltage (+3.3 V) output terminal
16
DVCC
-
Power supply terminal (+3.3 V)
17
DVSS
-
Ground terminal
18 to 25
D0 to D7
I/O
Two-way data bus with the S-RAM
26
DVSS
-
Ground terminal
27
DVCC
-
Power supply terminal (+3.3 V)
28 to 35
D8 to D15
I/O
Two-way data bus with the S-RAM
36
A0
O
Address signal output terminal Not used
37 to 43
A1 to A7
O
Address signal output to the S-RAM
44
DVSS
-
Ground terminal
45
DVCC
-
Power supply terminal (+3.3 V)
46 to 54
A8 to A16
O
Address signal output to the S-RAM
55 to 58
BUS0 to BUS3
O
Serial data output to the MP3 processor
59
/BUCK
O
Serial data transfer clock signal output to the MP3 processor
60
/CCE
O
Chip enable signal output to the MP3 processor
61
/RST
I
Reset signal input from the MP3 processor "L": reset
62
DVSS
-
Ground terminal
63
DVCC
-
Power supply terminal (+3.3 V)
64
RD
O
Output enable signal output to the S-RAM
65
WR
O
Write enable signal output to the S-RAM
66
SRLLB
O
Lower-byte control signal output to the S-RAM
67
SRLUB
O
Upper-byte control signal output to the S-RAM
68
NO USE
O
Not used
69
BOOT
I
Boot mode selection signal input terminal "L": boot mode
70
CS2
I
Chip select signal output to the S-RAM
71
LRCK
O
L/R sampling clock signal output to the MP3 processor
72
AM1
I
Function mode selection signal input terminal Fixed at "H" in this set
73
X2
O
System clock output terminal (9 MHz)
74
DVSS
-
Ground terminal
75
X1
I
System clock input terminal (9 MHz)
76
DVCC
-
Power supply terminal (+3.3 V)
77
USBOC
I
Over current detection signal input terminal
78
USBPON
O
USB VBUS power on/off control signal output terminal "H": power on
79
D+
I/O
Two-way data (positive) bus with the USB connector
80
D-
I/O
Two-way data (negative) bus with the USB connector
81
AM0
I
Function mode selection signal input terminal Fixed at "H" in this set
82
NO USE
O
Not used
83
DVSS
-
Ground terminal
84
DO
O
Clear to send signal output to the system controller
85
DATA
O
Serial data output terminal Not used
86
CLOCK
O
Serial data transfer clock signal output terminal Not used
87
TXD1
O
Serial data output to the system controller
88
RXD1
I
Serial data input from the system controller
89
NO USE
O
Not used
90
SDA
I/O
Two-way EEPROM IIC data bus terminal Not used
HCD-DH30
60
Pin No.
Pin Name
I/O
Description
91
SCL
I/O
Two-way EEPROM IIC clock bus terminal Not used
92
BCK
O
Bit clock signal output to the MP3 processor
93
DATA
O
Audio data output to the MP3 processor
94
GATE
O
Gate signal output to the MP3 processor
95
DVCC
-
Power supply terminal (+3.3 V)
96
REQ
I
Request signal input from the MP3 processor
97
ST-REQ
I
Request signal input from the MP3 processor
98, 99
G-1, G-2
I
Function selection signal input terminal Fixed at "L" in this set
100
DVSS
-
Ground terminal
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