Sony CDP-XE270 / CDP-XE370 Service Manual ▷ View online
21
CDP-XE270/XE370
IC131
CXA2581N-T4
RW/ROM
RW/ROM
EQ ON/OFF
VOFST
VOFST
DVC
VC
VC
VC
RW/ROM
VC
DVC
30
29
28
+
–
+
–
DVC
VCC
DVC
27
26
25
24
RW/ROM
EQ
23
22
21
20
19
RFAC
VCA
VCC
+
–
DVC
+
–
+
–
RW/ROM
VC
RW/ROM
DVC
+
–
3
A
B
C
D
B
C
C
A
A
A
B
C
C
D
B
C D
D
+
–
1
2
APC AMP
5
6
7
8
9
4
RFAC
SUMMING
AMP
RW/ROM
APC-OFF
(Hi-Z)
RW/ROM
(H/L)
VOFST
VC
RW/ROM
+
–
10
11
GM
GM
18
17
16
B
D
A
C
13
14
15
12
EQ IN
LD
PD
GND
A
B
C
D
AC SUM
E
F
DVCC
DVC
RFAC
SW
DC OFST
RFDCI
RFDCO
VC
RFC
VFC
BST
RFG
VCC
CEI
CE
TE BAL
TE
FEI
FE
– MAIN Board –
IC631
BA6956AN
1
2
3
4
5
6
7
8
9
CONTROL LOGIC
TSD
VREF
O
UT2
O
UT1
RNF
VM
VCC
FIN
GND
RIN
22
CDP-XE270/XE370
6-8.
IC PIN FUNCTION DESCRIPTION
•
Pin No.
Pin Name
I/O
Description
1
SQSO
O
Subcode Q data output to the system controller (IC501)
2
SQCK
I
Subcode Q data reading clock signal input from the system controller (IC501)
3
XRST
I
System reset signal input from the system controller (IC501) “L”: reset
4
SYSM
I
Analog line muting on/off control signal input terminal “H”: line muting on
Not used (fixed at “L”)
Not used (fixed at “L”)
5
DATA
I
Serial data input from the system controller (IC501)
6
XLAT
I
Serial data latch pulse signal input from the system controller (IC501)
7
CLOK
I
Serial data transfer clock signal input from the system controller (IC501)
8
SENS
O
Internal status (SENSE) output to the system controller (IC501)
9
SCLK
I
SENSE serial data reading clock signal input from the system controller (IC501)
10
VDD
—
Power supply terminal (+5V) (digital system)
11
ATSK
I/O
Input/output terminal for anti-shock Not used (pull down)
12
SPOA
I
Microcomputer escape interface input A terminal Not used (fixed at “L”)
13
SPOB
I
Microcomputer escape interface input B terminal Not used (fixed at “L”)
14
XLON
O
Microcomputer escape interface output terminal Not used (open)
15
WFCK
O
Write frame clock signal output terminal Not used (open)
16
XUGF
O
XUGF signal output terminal Not used (open)
17
XPCK
O
XPCK signal output terminal Not used (open)
18
GFS
O
Guard frame sync signal output terminal Not used (open)
19
C2PO
O
C2 pointer signal output terminal Not used (open)
20
SCOR
O
Subcode sync (S0+S1) detection signal output to the system controller (IC501)
21
COUT
I/O
Numbers of track counted signal input/output terminal Not used (open)
22
MIRR
I/O
Mirror signal input/output terminal Not used (open)
23
DFCT
I/O
Defect signal input/output terminal Not used (open)
24
FOK
I/O
Focus OK signal input/output terminal Not used (open)
25
LOCK
I/O
GFS is sampled by 460 Hz “H” when GFS is “H” Not used (open)
26
MDP
O
Spindle motor (M101) servo drive signal output to the AN4800SB (IC150)
27
SSTP
I
Detection signal input from limit in switch (S101)
The optical pick-up is inner position when “H”
The optical pick-up is inner position when “H”
28
SFDR
O
Sled servo drive PWM signal (+) output to the AN4800SB (IC150)
29
SRDR
O
Sled servo drive PWM signal (–) output to the AN4800SB (IC150)
30
TFDR
O
Tracking servo drive PWM signal (+) output to the AN4800SB (IC150)
31
TRDR
O
Tracking servo drive PWM signal (–) output to the AN4800SB (IC150)
32
FFDR
O
Focus servo drive PWM signal (+) output to the AN4800SB (IC150)
33
FRDR
O
Focus servo drive PWM signal (–) output to the AN4800SB (IC150)
34
VSS
—
Ground terminal (digital system)
35
TEST
I
Input terminal for the test (fixed at “L”)
36
TES1
I
Input terminal for the test (fixed at “L”)
37
XTSL
I
Input terminal for the system clock frequency setting
“L”: 16.9344 MHz, “H”: 33.8688 MHz (fixed at “L” in this set)
“L”: 16.9344 MHz, “H”: 33.8688 MHz (fixed at “L” in this set)
38
VC
I
Middle point voltage (+2.5V) input from the CXA2581N (IC131)
39
FE
I
Focus error signal input from the CXA2581N (IC131)
40
SE
I
Sled error signal input from the CXA2581N (IC131)
41
TE
I
Tracking error signal input from the CXA2581N (IC131)
42
CE
I
Middle point servo analog signal input from the CXA2581N (IC131)
43
RFDC
I
RF signal input from the CXA2581N (IC131)
BD BOARD IC101 CXD2587Q
(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR, DIGITAL FILTER, D/A CONVERTER)
(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR, DIGITAL FILTER, D/A CONVERTER)
23
CDP-XE270/XE370
Pin No.
Pin Name
I/O
Description
44
ADIO
O
Output terminal for the test Not used (open)
45
AVSS0
—
Ground terminal (digital system)
46
IGEN
I
Stabilized current input for operational amplifiers
47
AVDD0
—
Power supply terminal (+5V) (digital system)
48
ASYO
O
EFM full-swing output terminal
49
ASYI
I
Asymmetry comparator voltage input terminal
50
BIAS
I
Asymmetry circuit constant current input terminal
51
RFAC
I
EFM signal input from the CXA2581N (IC131)
52
AVSS3
—
Ground terminal (digital system)
53
CLTV
I
Internal VCO control voltage input
54
FILO
O
Filter output for master PLL
55
FILI
I
Filter input for master PLL
56
PCO
O
Charge pump output for master PLL
57
AVDD3
—
Power supply terminal (+5V) (digital system)
58
VSS
—
Ground terminal (digital system)
59
VDD
—
Power supply terminal (+5V) (digital system)
60
DOUT
O
Digital audio signal output to the DIGITAL OUT OPTICAL (IC651)
61
LRCK
O
D/A interface L/R sampling clock signal (44.1 kHz) output terminal Not used (open)
62
PCMD
O
D/A interface serial data output terminal Not used (open)
63
BCK
O
D/A interface bit clock signal (2.8224 MHz) output terminal Not used (open)
64
EMPH
O
“H” is output when playback disc is emphasis on
“L” is output when playback disc is emphasis off Not used (open)
“L” is output when playback disc is emphasis off Not used (open)
65
XVDD
—
Power supply terminal (+5V) (crystal oscillator system)
66
XTAI
I
System clock input terminal (16.9344 MHz)
67
XTAO
O
System clock output terminal (16.9344 MHz)
68
XVSS
—
Ground terminal (crystal oscillator system)
69
AVDD1
—
Power supply terminal (+5V) (analog system)
70
AOUT1
O
L-ch analog audio signal output
71
AIN1
I
L-ch operational amplifiers input
72
LOUT1
O
L-ch line output
73
AVSS1
—
Ground terminal (analog system)
74
AVSS2
—
Ground terminal (analog system)
75
LOUT2
O
R-ch line output
76
AIN2
I
R-ch operational amplifiers input
77
AOUT2
O
R-ch analog audio signal output
78
AVDD2
—
Power supply terminal (+5V) (analog system)
79
RMUT
O
R-ch line muting on/off control signal output “L”: line muting on
80
LMUT
O
L-ch line muting on/off control signal output “L”: line muting on
24
CDP-XE270/XE370
•
Pin No.
Pin Name
I/O
Description
1
NC
I
Connected to the ground
2
RMIN
I
Remote control signal input from the remote control receiver (IC561)
3
NC
I
Connected to the ground
4 to 6
NC
O
Not used (open)
7
LDON/RW/OFF
O
CD-ROM/RW selection signal output “L”: CD-ROM, “H”: CD-RW
8
CLK
O
Serial data transfer clock signal output to the CXD2587Q (IC101)
9
SENS
I
Internal status (SENSE) signal input from the CXD2587Q (IC101)
10
DATA
O
Serial data output to the CXD2587Q (IC101)
11
SQCK
O
Subcode Q data reading clock signal output to the CXD2587Q (IC101)
12
SQSO
I
Subcode Q data signal input from the CXD2587Q (IC101)
13, 14
NC
O
Not used (open)
15
XLAT
O
Serial data latch pulse signal output to the CXD2587Q (IC101)
16 to 19
NC
O
Not used (open)
20
LDOUT
O
Loading motor (M151) drive signal output to the BA6956AN (IC631) “H” active *1
21
LDIN
O
Loading motor (M151) drive signal output to the BA6956AN (IC631) “H” active *1
22, 23
NC
O
Not used (open)
24
KEY0
I
Key input terminal (A/D input)
S501 to S504 (TIME, PLAY MODE, CLEAR, REPEAT) keys input
S501 to S504 (TIME, PLAY MODE, CLEAR, REPEAT) keys input
25
KEY1
I
Key input terminal (A/D input) S520 (1/2) (l AMS L) keys input
26
KEY2
I
Key input terminal (A/D input) S520 (2/2) to S524, S526, S527
(l AMS L PUSH ENTER, A OPEN/CLOSE, H, X, x, M, m) keys input
(l AMS L PUSH ENTER, A OPEN/CLOSE, H, X, x, M, m) keys input
27
NC
O
Not used (open)
28
ADJ/AFADJ/BD
TEST
I
Setting terminal for the test mode
“L”: ADJ test mode, “M”: AFADJ test mode, “H”: BD test mode
“L”: ADJ test mode, “M”: AFADJ test mode, “H”: BD test mode
29
IN/OUT SW
I
Loading in detect switch (S152) and loading out detect switch (S151) input terminal
“L”: load in, “H”: load out
“L”: load in, “H”: load out
30
RST
I
System reset signal input from the reset signal generator (IC603) “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
31
EXTAL
I
Main system clock input terminal (4 MHz)
32
XTAL
O
Main system clock output terminal (4 MHz)
33
VSS
—
Ground terminal
34 to 41
NC
O
Not used (open)
42 to 47
S6 to S1
O
Segment drive signal output to the fluorescent indicator tube (FL501)
48 to 55
S7, S11, S12, S8,
S21, S10, S9, S20
O
Segment drive signal output to the fluorescent indicator tube (FL501)
56 to 62
S13 to S19
O
Segment drive signal output to the fluorescent indicator tube (FL501)
63 to 67
7G to 3G
O
Grid drive signal output to the fluorescent indicator tube (FL501)
68
NC
O
Not used (open)
69, 70
2G, 1G
O
Grid drive signal output to the fluorescent indicator tube (FL501)
71
VFDP (–30V)
—
Power supply terminal (–30V) (for fluorescent indicator tube drive)
72
VDD (+5V)
—
Power supply terminal (+5V)
DISPLAY BOARD IC501 CXP82324-093Q
(SYSTEM CONTROLLER, FLUORESCENT INDICATOR TUBE DRIVER, KEY CONTROL)
(SYSTEM CONTROLLER, FLUORESCENT INDICATOR TUBE DRIVER, KEY CONTROL)
*1 Loading motor (M151) control
OFF
OUT
IN
BRAKE
LDIN (pin wa)
“L”
“L”
“H”
“H”
LDOUT (pin w;)
“L”
“H”
“L”
“H”
Operation
Terminal
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