Sony CDP-CX53 Service Manual ▷ View online
– 35 –
• IC Block Diagrams
IC101
LA9241M (BD Board)
IC102
LC78622E (BD Board)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64
VCC1
LDS
LDD
BHI
PHI
LF2
VR
REFI
VCC2
FSS
DRF
CE
DAT
CL
CLK
DEF
FD-
FA
FA-
FE
FE-
SL-
SL+
AGND
SP
SPI
SPG
SP-
SPD
SLEQ
SLD
JP-
NC
TBC
FSC
DGND
SLI
SLC
RFS-
RFSM
CV+
CV-
CV-
SLOF
HFL
TES
TOFF
TOFF
TGL
JP+
FIN2
FINI
E
F
TB
TE-
TE
TESI
SCI
TH
TA
TD-
TD
JR
TO
FD
62
61
60
59
55 54 53 52 51 50
49
48
47
46
45
44
43
41
40
39
38
37
37
36
35
34
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
42
58
57
56
RF DET
I / V
VCA
VCA
LSC
RF AMP
BAL
TE
T. SERVO & T. LOGIC
F. SERVO & F. LOGIC
SPINDLE SERVO
SLED SERVO
µ
-COM
INTERFACE
APC
REF
+ -
+
-
+
-
+
-
+ -
+ -
+ -
- +
+ -
63
DEFI
EFLG
SBSY
XVSS
XIN
XOUT
XVDD
MUTER
RVDD
RVDD
RCHO
RVSS
LVSS
LCHO
RVSS
LVSS
LCHO
LVDD
MUTEL
N.C
MUTEL
N.C
TEST4
TAI
PDO
VVSS
ISET
VVDD
FR
VSS
EFMO
EFMIN
TEST2
CLV+
CLV-
V / P
HFL
TES
SLICE LEVEL
CONTROL
µ
COM
INTERFACE
XTAL
TIMING GENERATOR
2K x 8BIT
RAM
RAM ADDRESS
GENERATOR
MUTE
SERVO
COMMANDER
CLV
DIGITAL SERVO
DIGITAL
ATTENUATOR
OVERSAMPLING
DIGITAL FILTER
1BIT DAC
L.P.F
DIGITAL OUT
GENERAL PORT
VCO CLOCK OSCILLATION
CLOCK CONTROL
SYNCRONOUS DETECTION
EFM DEMODULATION
SUBCODE CLASSIFICATION
QCRC
64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
28
18 19 20 21
23 24 25 26 27
29
30
31
32
63
62
61
60
59 58 57 56 55 54 53 52
51
50
49
48
47
45
46
44
42
43
33
34
41
40
40
39
38
37
36
36
35
22
TEST1
CS
TEST5
RES
TEST1
16M
4.2M
COCK
COIN
SQOUT
RWC
WRQ
FSX
SBCK
SFSY
PW
EMPH
CF2
DOUT
TGL
TOFF
TEST3
JP+
JP-
PCK
FSEQ
VDD
CONT1
CONT2
CONT3
CONT4
CONT5
C1, C2
ERROR DETECTION
&
CORRECTION
FLAG PROTCESS
– 36 –
IC103
LA6541 (BD Board)
IC701
LA5602 (AUDIO Board)
IC703
LA5601 (AUDIO Board)
IC601
BA6780 (AUDIO Board)
VCC
MUTE
VINL
VGL
VO1
VO2
VCC
VIN4
VG4
VO8
VO7
VREF
11k
Ω
11k
Ω
11k
Ω
11k
Ω
1
1
2
3
4
5
6
VO3
VO4
VG2
VIN2
REG OUT
REG IN
7
8
9
10
11
12
24
23
22
21
20
19
VO6
VO5
VG3
VIN3
CD
RES
18
17
16
15
14
13
+
-
+
-
LEVEL
SHIFT
LEVEL
SHIFT
BTL
DRIVER
BTL
DRIVER
BTL
DRIVER
BTL
DRIVER
LEVEL
SHIFT
LEVEL
SHIFT
REGULATOR
RESET
Vcc
1
2
3
4
5
7
6
V IN
EN
GND
CDEL
CN
RES
V OUT
REFERENCE
VOLTAGE
OVER HEAT
PROTECTION
OVER CURRENT
LIMITTER
ON/OFF
RESET
GEN
ERROR
AMP
VIN2
FIN2
RIN2
CT2
VEE
FBIN-
FBIN+
OUT2+
OUT2-
VIN1
FIN1
REVERSIBLE DRIVER
FWD/REV CONTROLLER
COVERNER DRIVER
FWD/REV CONTROLLER
COVERNER
LOAD CURRENT
DETECTION
AMPLIFIER
COVERNER
OUTPUT
REFERENCE
VOLTAGE OUTPUT
LOW VOLTAGE
OUTPUT
RIN1
IOUT
VEE
VEE
VCC
VREF
VREG
VCC
OUT1+
+-
OUT1-
18
17
16
15
1
2
3
4
5
6
7
8
9
14
13
12
11
10
3
6
7
2
5
1
4
9
8
10
ON/OFF
AMP
V REF
AMP
RESET
VOMUTE
CD
VIN
VO
RES
CN
GND
EN
VID
VOD
– 37 –
7-9.
IC PIN FUNCTION DESCRIPTION
•
BD BOARD IC101 LA9241M (RF AMPLIFIER, FOCUS/TRACKING/SLED SERVO)
Pin No.
Pin Name
I/O
Function
1
FIN2
I
Signal input (B+D) from the optical pick-up detector
Added with FIN1 to create RF signal, subtracted with FIN1 to create focus error signal
Added with FIN1 to create RF signal, subtracted with FIN1 to create focus error signal
2
FIN1
I
Signal input (A+C) from the optical pick-up detector
3
E
I
Signal input (E) from the optical pick-up detector
Subtracted with F to create tracking error signal
Subtracted with F to create tracking error signal
4
F
I
Signal input (F) from the optical pick-up detector
5
TB
I
Tracking error signal input for the tracking balance adjustment
6
TE–
I
Tracking error signal (invert signal) input terminal
7
TE
O
Tracking error signal output terminal
8
TESI
I
TES (Track Error Sense) comparator input terminal
Tracking error signal is band-passed and input
Tracking error signal is band-passed and input
9
SCI
I
Shock detection input terminal
10
TH
I
Time constant setting terminal for the tracking gain adjustment
11
TA
O
TA amplifier output terminal
12
TD–
I
Creates a tracking phase compensation constant between TD (pin !£) and VR (pin %•) pins
13
TD
O
Setting terminal for the tracking phase compensation
14
JP
I
Setting terminal for the tracking jump signal (kick pulse) amplitude
15
TO
O
Tracking coil (2-axis device) drive signal output to the LA6541 (IC103), and sled motor drive
signal output terminal
signal output terminal
16
FD
O
Focus coil (2-axis device) drive signal output to the LA6541 (IC103)
17
FD–
I
Creates a focusing phase compensation constant between FD (pin !§) and FA (pin !•) pins
18
FA
O
Creates a focusing phase compensation constant between FD– (pin !¶) and FA– (pin !ª) pins
19
FA–
I
Creates a focusing phase compensation constant between FA (pin !•) and FE (pin @º) pins
20
FE
O
Focus error signal output terminal
21
FE–
I
Focus error signal (invert signal) input terminal
22
AGND
—
Ground terminal (analog system)
23
SP
O
Single end output of the CV+ (pin $º) and CV– (pin #ª) pins signal
24
SPI
I
Spindle amplifier input terminal (invert input)
25
SPG
I
Gain setting resistor is connected when the spindle 12 cm mode
26
SP–
I
Works together with the SPD (pin @¶) to connect to the spindle phase compensation constant
27
SPD
O
Spindle motor (M101) drive signal output to the LA6541 (IC103)
28
SLEQ
I
Sled phase compensation constant is connected
29
SLD
O
Sled motor (M102) drive signal output to the LA6541 (IC103)
30
SL–
I
Sled feeding signal input from the system controller (IC801)
31
SL+
I
Sled feeding signal input from the system controller (IC801)
32
JP–
I
Tracking jump control signal input from the DSP (IC102)
33
JP+
I
Tracking jump control signal input from the DSP (IC102)
34
TGL
I
Tracking gain control signal input from the DSP (IC102) Gain becomes low when TGL is “H”
35
TOFF
I
Tracking off control signal input from the DSP (IC102)
Tracking becomes off when TOFF is “H”
Tracking becomes off when TOFF is “H”
36
TES
O
Tracking error signal output to the DSP (IC102)
37
HFL
O
Tracking detection signal output to the DSP (IC102) HFL (High Frequency Level) is used to
determine whether the main beam is positioned on a pit or a mirror
determine whether the main beam is positioned on a pit or a mirror
38
SLOF
I
Sled servo off control signal input from the DSP (IC102) Rough servo/phase control automatic
switching monitor input “H”: rough servo, “L”: phase servo
switching monitor input “H”: rough servo, “L”: phase servo
39
CV–
I
CLV error signal input from the DSP (IC102)
– 38 –
Pin No.
Pin Name
I/O
Function
40
CV+
I
CLV error signal input from the DSP (IC102)
41
RFSM
O
Playback EFM RF signal output to the DSP (IC102)
42
RFS–
I
Works together with the RFSM (pin $¡) to set the RF gain and the 3T compensation constant for
the EFM RF signal
the EFM RF signal
43
SLC
O
SLI (Slice Level Control) is output to control a data slice level of the RF waveform by the DSP
(IC102)
(IC102)
44
SLI
I
Input terminal for controlling a data slice level by the DSP (IC102)
45
DGND
—
Ground terminal (digital system)
46
FSC
O
Focus search smoothing capacitor output terminal
47
TBC
I
TBC (Tracking Balance Control) sets a EF balance variable range
48
NC
—
Not used (open)
49
DEF
O
Defect detection signal output to the DSP (IC102)
50
CLK
I
Reference clock (4.2336 MHz) input from the DSP (IC102)
51
CL
I
Command serial clock signal input from the system controller (IC801)
52
DAT
I
Command serial data input from the system controller (IC801)
53
CE
I
Command chip enable signal input from the system controller (IC801)
54
DRF
O
RF level detection signal output to the system controller (IC801)
55
FSS
I
FSS (Focus Search Select) is a switching terminal for the focus search mode (
±
search/+search for
a reference voltage) Not used (open)
56
VCC2
—
Power supply terminal (+5V) (servo system and digital system)
57
REFI
I
Connected to the coupling capacitor for the reference voltage (+2.5V)
58
VR
O
Reference voltage (+2.5V) output terminal
59
LF2
I
Constant setting for a disc defect detection
60
PH1
I
Connected to the capacitor for the RF signal peak hold
61
BH1
I
Connected to the capacitor for the RF signal bottom hold
62
LDD
O
Laser drive signal output to the automatic power control circuit
63
LDS
I
Light amount monitor input of the laser diode (PD)
64
VCC1
—
Power supply terminal (+5V) (RF system)
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