Sony CDP-CX300 / CDP-CX350 / CDP-CX691 Service Manual ▷ View online
– 53 –
• BD section
7-22. IC BLOCK DIAGRAMS
IC101 CXD2587Q
TE
RFDC
CE
IGEN
AVSS0
ADIO
AVDD0
CLTV
FILO
AVSS3
VSS
AVDD3
DOUT
VDD
PCO
FILI
ASYO
ASYI
RFAC
BIAS
SSTP
DFCT
MIRR
MDP
LOCK
FOK
SFDR
VSS
TEST
FRDR
FE
VC
VC
COUT
SE
XTSL
TES1
SRDR
TFDR
FFDR
TRDR
TRDR
2
1
70
71
68
69
66
67
64
65
62
61
63
73
74
72
75
76
77
78
79
80
4
XRST
3
SQCK
SQSO
5
9
8
7
6
56
60
53
54
55
59
57
58
51
52
48
49
50
47
44
45
46
43
41
42
XLAT
CLOK
SENS
SYSM
DATA
XUGF
XPCK
GFS
C2PO
WFCK
10 11 12 13 14 15 16 17 18 19 20
21
22
23
24
25
26
32
33
30
31
36
37
34
35
39
40
38
28
27
29
SPOA
ATSK
SCLK
VDD
SCOR
SPOB
XLON
XTAI
XVDD
EMPH
AVDD1
AOUT1
AIN1
XTAO
XVSS
XVSS
AIN2
AOUT2
AVDD2
RMUT
LOUT2
LOUT1
BCK
LRCK
PCMD
LMUT
AVSS1
AVSS2
CPU
INTERFACE
SERVO AUTO
SEQUENCER
SERIAL IN
INTERFACE
OVER SAMPLING
DIGITAL FILTER
3rd ORDER
NOISE SHAPER
PWM
PWM
EFM
DEMODULATOR
TIMING
LOGIC
DIGITAL
OUT
D/A
INTERFACE
DIGITAL
PLL
ASYMMETRY
CORRECTION
CORRECTION
CLOCK
GENERATOR
MIRR, DFCT,
FOK
DETECTOR
DIGITAL
CLV
SUBCODE
PROCESSOR
SERVO
INTERFACE
SERVO DSP
FOCUS
SERVO
SERVO
TRACKING
SERVO
SLED
SERVO
PWM GENERATOR
FOCUS PWM
GENERATOR
TRACKING
PWM GENERATOR
SLED PWM
GENERATOR
16K
RAM
ERROR
CORRECTOR
INTERNAL BUS
A/D
CONVERTER
OPERATIONAL
AMPLIFIER
ANALOG SWITCH
IC102 BA6392FP-E2
BUFF
BUFF
BUFF
BUFF
R
R
F
F
1
CH1 OUT F
2
CH1 OUT R
3
CAPA IN 1
4
CH1 R IN
5
CH1 F IN
6
VREF IN
7
VREF OUT
8
GND
9
CH2 F IN
10
CH2 R IN
11
CAPA IN 2
12
CH2 OUT R
13
CH2 OUT F
14
GND
28 GND
27 CH4 OUT F
26 CH4 OUT R
25 VB IN
24 VS IN
23 VB IN
22 VCC
21 VCC
20 CH3 F IN
19 CH3 R IN
18 CAPA IN 3
17 CH3 OUT R
16 CH3 OUT F
15 MUTE
LEVEL
SHIFT
INTERFACE
BUFF
BUFF
BUFF
BUFF
R
F
R
F
BUFF
INTERFACE
INTERFACE
F
F
R
R
MUTE
– 54 –
11
12
10
VC
VC
VC
VC
VC
VC
VC
VCC
VCC
RF SUMMING AMP RF_EQ_AMP
ERROR AMP
FOCUS
FOCUS
TRACKING
ERROR AMP
ERROR AMP
VC BUFFER
VCC
VCC
VC
VC
VC
VC
VEE
VEE
VEE
VEE
VEE
VREF
13
14
15
6
5
1
2
3
4
7
8
9
16
19
20
21
22
23
24
18
17
HOLD
LD
PD
A
B
C
D
VEE
F
E
VC
AGCVTH
AGCCONT
VCC
LC/PD
LD_ON
LD_ON
HOLD_SW
RF_BOT
RFTC
RF_1
RFO
RFO
RFE
FE
TE
(50%/30%
OFF)
OFF)
APC PD AMP
APC LD AMP
IC103 CXA2568M-T6
• Main section
IC504 M5M5256DFP-70XL
VCC
W
A13
A8
A9
A11
OE
A10
SI
DQ8
DQ7
DQ6
DQ5
DQ4
A12
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
GND
A7
A14
CLOCK
GENERATOR
OUTPUT
BUFFER
SENSE
AMP
32768 WORD
x 8 BIT
RAM
(512 x 512)
ROW
ADDRESS
DECODER
DECODER
ROW INPUT BUFFER
COLUMN INPUT BUFFER
COLUMN
ADDRESS
DECODER
DECODER
INPUT
DATA
CONTROL
1
2 3 4
5 6 7
8 9 10
11 12 13 14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
– 55 –
IC505 LA6510
IC931 LA5601
24
0
D
R
CK
23
0
D
R
CK
22
0
D
R
CK
21
0
D
R
CK
20
0
D
R
CK
19
0
D
R
CK
18
0
D
R
CK
17
0
D
R
CK
16
0
D
R
CK
15
0
D
R
CK
14
0
D
R
CK
13
4
5
6
7
8
9
10
11
12
0
D
R
CK
1
D
R
CK
1
D
R
CK
1
D
R
CK
1
D
R
CK
1
D
R
CK
1
D
R
CK
1
D
R
CK
1
D
R
CK
1
D
R
CK
1
D
R
CK
1
D
R
CK
1
D
R
CK
D
1
R
CK
D
1
0
0
R
CK
D
R
CK
D
R
CK
1
2
3
D
1
R
CK
D
1
0
0
R
CK
D
R
CK
D
R
CK
QC
QD
QE
QF
QG
QH
QI
QJ
QK
QL
QM
QN
QA
QB
VCC
D
ATA
OE
LT
RST
CLK
GND
SQP
QO
QP
IC702 M66310FP
• Display section
3
6
7
2
5
1
4
9
8
10
ON/OFF
AMP
V REF
AMP
RESET
VOMUTE
CD
VIN
VO
RES
CN
GND
EN
VID
VOD
VOUT1
+VIN1
VSENCE1
–VIN1
–VIN2
VCC
+VIN2
VOUT2
VSENCE2
VEE
1
2 3 4 5 6 7 8 9 10
+
–
+
–
– 56 –
7-23. IC PIN FUNCTIONS
• IC101 DIGITAL SIGNAL PROCESSOR (CXD2587Q) (BD board)
SQSO
SQCK
XRST
SYSM
DATA
XLAT
CLOK
SENS
SCLK
VDD
ATSK
SPOA
SPOB
XLON
WFCK
XUGF
XPCK
GFS
C2PO
SCOR
COUT
MIRR
DFCT
FOK
LOCK
MDP
SSTP
SFDR
SRDR
TFDR
TRDR
FFDR
FRDR
VSS
TEST
TES1
XTSL
VC
FE
SE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
O
I
I
I
I
I
I
O
I
–
I/O
I
I
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
O
I
O
O
O
O
O
O
–
I
I
I
I
I
I
Sub-Q 80-bit and PCM peak level data output (CD text data output)
Clock input for SQSO read-out
System reset
“L” : reset
Muting input “H” : mute
Serial data input, supplied from CPU
Latch input, supplied from CPU
Serial data transfer clock input, supplied from CPU
SENS signal output to CPU
SENS serial data read-out clock input
Digital power supply
Input pin for anti-shock (Connected to ground)
Microcomputer escape interface input A
Microcomputer escape interface input B
Microcomputer escape interface output
WFCK output (Not used)
Not used
Not used
Not used
Not used
Sub-code sync output
Numbers of track counted signal input/output (Not used)
Mirror signal input/output (Not used)
Defect signal input/output (Not used)
Focus OK input/output (Not used)
GFS is sampled by 460 Hz. H when GFS is H (Not used)
Output to control spindle motor servo
Input signal to detect disc inner most track
Sled drive output
Sled drive output
Tracking drive output
Tracking drive output
Focus drive output
Focus drive output
Digital ground
TEST pin connected normally to ground
TEST pin connected normally to ground
X'tal selection input (Connected to ground)
Center voltage input pin
Focus error signal input
Sled error signal input
Pin No.
Pin Name
I/O
Function
• Abbreviation
GFS : Guarded Frame Sync
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