Sony CDP-CE575 Service Manual ▷ View online
CDP-CE575
29
29
• IC Block Diagrams
– BD Board –
– BD Board –
IC101
CXD2587Q
TE
RFDC
CE
IGEN
AVSS0
ADIO
AVDD0
CLTV
FILO
AVSS3
VSS
AVDD3
DOUT
VDD
PCO
FILI
ASYO
ASYI
RFAC
BIAS
SSTP
DFCT
MIRR
MDP
LOCK
FOK
SFDR
VSS
TEST
FRDR
FE
VC
VC
COUT
SE
XTSL
TES1
SRDR
TFDR
FFDR
TRDR
TRDR
2
1
70
71
68
69
66
67
64
65
62
61
63
73
74
72
75
76
77
78
79
80
4
XRST
3
SQCK
SQSO
5
9
8
7
6
56
60
53
54
55
59
57
58
51
52
48
49
50
47
44
45
46
43
41
42
XLAT
CLOK
SENS
SYSM
DATA
XUGF
XPCK
GFS
C2PO
WFCK
10 11 12 13 14 15 16 17 18 19 20
21
22
23
24
25
26
32
33
30
31
36
37
34
35
39
40
38
28
27
29
SPOA
ATSK
SCLK
VDD
SCOR
SPOB
XLON
XTAI
XVDD
EMPH
AVDD1
AOUT1
AIN1
XTAO
XVSS
XVSS
AIN2
AOUT2
AVDD2
RMUT
LOUT2
LOUT1
BCK
LRCK
PCMD
LMUT
AVSS1
AVSS2
CPU
INTERFACE
SERVO AUTO
SEQUENCER
SERIAL IN
INTERFACE
OVER SAMPLING
DIGITAL FILTER
3rd ORDER
NOISE SHAPER
PWM
PWM
EFM
DEMODULATOR
TIMING
LOGIC
DIGITAL
OUT
D/A
INTERFACE
DIGITAL
PLL
ASYMMETRY
CORRECTION
CORRECTION
CLOCK
GENERATOR
MIRR, DFCT,
FOK
DETECTOR
DIGITAL
CLV
SUBCODE
PROCESSOR
SERVO
INTERFACE
SERVO DSP
FOCUS
SERVO
SERVO
TRACKING
SERVO
SLED
SERVO
PWM GENERATOR
FOCUS PWM
GENERATOR
TRACKING
PWM GENERATOR
SLED PWM
GENERATOR
16K
RAM
ERROR
CORRECTOR
INTERNAL BUS
A/D
CONVERTER
OPERATIONAL
AMPLIFIER
ANALOG SWITCH
IC131
CXA2581N-T4
IC11
BA6780
VIN2
FIN2
RIN2
CT2
VEE
FBIN-
FBIN+
OUT2+
OUT2-
VIN1
FIN1
REVERSIBLE DRIVER
FWD/REV CONTROLLER
COVERNER DRIVER
FWD/REV CONTROLLER
COVERNER
LOAD CURRENT
DETECTION
AMPLIFIER
COVERNER
OUTPUT
REFERENCE
VOLTAGE OUTPUT
LOW VOLTAGE
OUTPUT
RIN1
IOUT
VEE
VEE
VCC
VREF
VREG
VCC
OUT1+
+-
OUT1-
18
17
16
15
1
2
3
4
5
6
7
8
9
14
13
12
11
10
– JUNCTION Board –
RW/ROM
RW/ROM
EQ ON/OFF
VOFST
VOFST
DVC
VC
VC
VC
RW/ROM
VC
DVC
30
29
28
+
–
+
–
DVC
VCC
DVC
27
26
25
24
RW/ROM
EQ
23
22
21
20
19
RFAC
VCA
VCC
+
–
DVC
+
–
+
–
RW/ROM
VC
RW/ROM
DVC
+
–
3
A
B
C
D
B
C
C
A
A
A
B
C
C
D
B
C D
D
+
–
1
2
APC AMP
5
6
7
8
9
4
RFAC
SUMMING
AMP
RW/ROM
APC-OFF
(Hi-Z)
RW/ROM
(H/L)
VOFST
VC
RW/ROM
+
–
10
11
GM
GM
18
17
16
B
D
A
C
13
14
15
12
EQ IN
LD
PD
GND
A
B
C
D
AC SUM
E
F
DVCC
DVC
RFAC
SW
DC OFST
RFDCI
RFDCO
VC
RFC
VFC
BST
RFG
VCC
CEI
CE
TE BAL
TE
FEI
FE
CDP-CE575
30
30
7-9.
PRINTED WIRING BOARDS – DISPLAY Section –
•
See page 21 for Circuit Boards Location.
CNP801
S846
CN811
S821
S815
S814
S822
S813
S823
S812
S824
S825
S811
IC802
Q807
D801
CN812
Q801
Q802
Q803
R803
R802
R801
R851
C801
C855
C854
C853
C852
C803
R823
R811
R812
R813
R814
R815
R846
R822
R824
R821
R816
R852
R853
R855
R854
R807
Q806
Q804
Q805
C861
R804
R805
C862
R862
R806
R861
FL801
FLUORESCENT INDICATOR TUBE
JW4
JW5 JW6
JW7
JW8
JW9
JW10
JW11
JW12
JW13
JW14
JW15
JW16
JW17
IC801
CNP812
R841
R842
R843
R844
R845
S844
S845
S843
S842
S841
R835
CNP811
S831
S832
S833
S834
S835
S836
S837
S838
S827
S826
R831
R832
R833
R834
R825
R826
R837
R836
DISPLAY BOARD
C
MAIN BOARD
CN801
S801
ROTARY ENCODER
.
AMS >
(DISC)
PUSH ENTER
A
OPEN/CLOSE
3
1
E
D801, S821
MEGA CONTROL
DISC
SKIP
SKIP
EX-CHANGE
X-FADE
NO DELAY
s
MENU
m
(AMS–)
M
(AMS+)
X
H
E
E
E
1 2
5
55
58 59
E
E
E
1
3
4
1
1-681-133-
11
(11)
21
(21)
(US, CND)
(AEP)
S811-815, 821-827,
S831-838, 841-846
1
3
KEY(B) BOARD
FADER
PEAK
SEARCH
CLEAR
CHECK
EDIT
1-681-137-
11
(11)
21
(21)
(US, CND)
(AEP)
KEY(A) BOARD
TIME/TEXT
DISC 5
DISC 4
DISC 3
DISC 2
DISC 1
REPEAT
PROGRAM
SHUFFLE
CONTINUE
1-681-134-
11
(11)
21
(21)
(US, CND)
(AEP)
A
B
C
D
1
2
3
4
5
6
7
8
9
10
11
12
• Semiconductor
Location
Ref. No.
Location
D801
B-3
IC801
A-8
IC802
B-12
Q801
A-6
Q802
A-6
Q803
A-6
Q804
A-12
Q805
A-12
Q806
A-12
Q807
B-2
(Page 28)
CDP-CE575
31
31
7-10. SCHEMATIC DIAGRAM – DISPLAY Section –
•
See page 32 for Waveform.
(Page 26)
CDP-CE575
32
32
1
IC101
ta
(RFAC) (CD Play Mode)
6
IC101
w;
(SCOR) (CD Play Mode)
qa
IC301
es
(XTAL)
2
IC101
rd
(RFDC) (CD Play Mode)
7
IC101
yj
(XTAO) (CD Play Mode)
qs
IC801
t;
(OSCO)
3
IC101
el
(FE) (CD Play Mode)
4
IC101
ra
(TE) (CD Play Mode)
• Waveforms
– BD Board –
– BD Board –
5
IC101
wh
(MDP) (CD Play Mode)
– MAIN Board –
– DISPLAY Board –
1.3 Vp-p
5.2 Vp-p
13.4 ms
5 Vp-p
100 ns
1.4 Vp-p
5.9 Vp-p
59 ns
2.3 Vp-p
508 ns
approx.
200 mVp-p
200 mVp-p
approx.
400 mVp-p
400 mVp-p
2.7 V
7.5
µ
s
7-11.
IC PIN FUNCTION DESCRIPTION
•
Pin No.
Pin Name
I/O
Description
1
SQSO
O
Subcode Q data output to the system controller (IC301)
2
SQCK
I
Subcode Q data reading clock signal input from the system controller (IC301)
3
XRST
I
System reset signal input from the system controller (IC301) “L”: reset
4
SYSM
I
Analog line muting on/off control signal input terminal “H”: line muting on
Not used (fixed at “L”)
Not used (fixed at “L”)
5
DATA
I
Command serial data input from the system controller (IC301)
6
XLAT
I
Command latch pulse input from the system controller (IC301)
7
CLOK
I
Command serial data transfer clock signal input from the system controller (IC301)
8
SENS
O
Internal status monitor output to the system controller (IC301)
9
SCLK
I
SENSE serial data reading clock input from the system controller (IC301)
10
VDD
—
Power supply terminal (+5V) (digital system)
11
ATSK
I/O
Input pin for anti-shock Not used (fixed at “L”)
12
SPOA
I
Microcomputer escape interface input A terminal Not used (fixed at “L”)
13
SPOB
I
Microcomputer escape interface input B terminal Not used (fixed at “L”)
14
XLON
O
Microcomputer escape interface output terminal Not used (open)
15
WFCK
O
WFCK output terminal Not used (open)
16
XUGF
O
Not used (open)
17
XPCK
O
Not used (open)
18
GFS
O
Not used (open)
19
C2PO
O
Not used (open)
20
SCOR
O
Subcode sync (S0+S1) detection signal output to the system controller (IC301)
21
COUT
I/O
Numbers of track counted signal input/output terminal Not used (open)
22
MIRR
I/O
Mirror signal input/output terminal Not used (open)
23
DFCT
I/O
Defect signal input/output terminal Not used (open)
24
FOK
I/O
Focus OK input/output terminal Not used (open)
25
LOCK
I/O
GFS is sampled by 460 Hz “H” when GFS is “H” Not used (open)
26
MDP
O
Spindle motor (M101) servo drive signal output to the AN48005B (IC150)
27
SSTP
I
Limit in detect switch (S101) input terminal
28
SFDR
O
Sled servo drive PWM signal (+) output to the AN48005B (IC150)
29
SRDR
O
Sled servo drive PWM signal (–) output to the AN48005B (IC150)
30
TFDR
O
Tracking servo drive PWM signal (+) output to the AN48005B (IC150)
31
TRDR
O
Tracking servo drive PWM signal (–) output to the AN48005B (IC150)
32
FFDR
O
Focus servo drive PWM signal (+) output to the AN48005B (IC150)
33
FRDR
O
Focus servo drive PWM signal (–) output to the AN48005B (IC150)
34
VSS
—
Ground terminal (digital system)
35
TEST
I
Input terminal for the test (fixed at “L”)
36
TES1
I
Input terminal for the test (fixed at “L”)
37
XTSL
I
Input terminal for the system clock frequency setting “L”: 45.1584 MHz, “H”: 22.5792 MHz
(fixed at “L” in this set)
(fixed at “L” in this set)
38
VC
I
Middle point voltage (+2.5V) input from the CXA2581N (IC131)
39
FE
I
Focus error signal input from the CXA2581N (IC131)
40
SE
I
Sled error signal input from the CXA2581N (IC131)
41
TE
I
Tracking error signal input from the CXA2581N (IC131)
42
CE
I
Command chip enable signal input from the CXA2581N (IC131)
BD BOARD IC101 CXD2587Q
(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR, DIGITAL FILTER, D/A CONVERTER)
(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR, DIGITAL FILTER, D/A CONVERTER)
Click on the first or last page to see other CDP-CE575 service manuals if exist.