Sony BMZ-K2 / CX-BK2 Service Manual ▷ View online
65
CX-BK2
•
MAIN BOARD IC901 uPD703260YGF-S04-JBT-A (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
RDS_SIG
I
Tuning signal level input terminal Not used
2
RDS_DATA
I
Serial data input terminal Not used
3
AVREF0
—
Reference voltage (+3.1V) input terminal
4
AVSS
—
Ground terminal
5
MICS
O
Chip select signal output to the MP3 decoder
6
DO
I
Serial data input from the tuner unit
7
AVREF1
—
Power supply terminal (+3.1V)
8
STEREO
I
Stereo detection signal input from the tuner unit
9
TUNE
I
Tuner tuned status signal from the tuner unit
10
FLMD0
—
Not used
11
VDD
—
Power supply terminal (+3.1V)
12
REGC
—
Connected to the external capacitor
13
VSS
—
Ground terminal
14
X1
I
Main system clock input terminal (5MHz)
15
X2
O
Main system clock output terminal (5MHz)
16
RESET
I
Reset signal input from the reset signal generator “L”: reset
17
XT1
I
Sub system clock input terminal (32.768kHz)
18
XT2
O
Sub system clock output terminal (32.768kHz)
19
MP3RST
O
System reset signal output to the MP3 decoder
20
RDS_CLK
I
Clock signal input Not used
21
SCOR
I
SCOR signal input from the digital signal processor
22
CAN'T_USE
—
Not used
23
RMC
I
Remote control signal input from the remote control receiver
24
USB_DATA
I/O
I2C data input/output with the USB interface IC
25
USB_CLK
I/O
I2C clock signal input/output to the USB interface IC
26
DECK_PLAYSW
I
PLAY switch signal input terminal Not used
27
DECK_ENDSW
I
END switch signal input terminal Not used
28
DECK_PACK
I
PACK switch signal input terminal Not used
29
DECK_FREC
I
Record protect detect switch signal input terminal Not used
30
DECK_RREC
I
Record protect detect switch signal input terminal Not used
31
USB_ACK
I
Acknowledge signal input from the USB interface IC
32
USB_INT
I
Interrupt request signal input from the USB interface IC
33
USB_VBUS_ON
O
VBUS control signal output terminal
34
STBY
O
Standby LED control signal output terminal
35
EVSS
—
Ground terminal
36
EVDD
—
Power supply terminal (+3.1V)
37
MIACK
I
Acknowledge signal input from the MP3 decoder
38
MP3STB
O
Strobe signal output to the MP3 decoder
39
MUTE
O
Muting control signal output to power amplifier circuit
40
POWER
O
Main power control signal output terminal
41
POWER_DOWN
I
Power down detection signal input terminal
42
HEADPHONE
I
Headphone detection signal input “L”: headphone on
43
SHIFT_CLK
O
Serial data transfer clock signal output to the shift register
44
SHIFT_DATA
O
Serial data output to the shift register
45
SHIFT_STB
O
Strobe signal output to the shift register
66
CX-BK2
Pin No.
Pin Name
I/O
Description
46
PLLCE
O
Latch signal output to the tuner unit
47
PWM1
O
PWM signal output for focus offset adjustment
48
MCLK
O
Serial data transfer clock signal output to the tuner unit and input select IC
49
PWM3
O
PWM signal output for RF offset adjustment
50
MDATA
O
Serial data output to the tuner unit and input select IC
51
PWM2
O
PWM signal output for tracking offset adjustment
52
DATA
O
Serial data output to the digital signal processor
53
LCD_DATA
O
Serial data output to the LCD driver
54
LCD_CLK
O
Serial data transfer clock output to the LCD driver
55
CLOCK
O
Serial data transfer clock output to the digital signal processor
56
SQSO
I
Sub-Q data input from the digital signal processor
57
SQCK
O
Sub-Q clock output to the digital signal processor
58
SENS
I
SENS signal input from the digital signal processor
59
LDON
O
Laser diode on/off control signal output to the automatic power control circuit “H”: laser on
60
XLT
O
Control data latch signal output to the digital signal processor
61
XRST
O
System reset signal output to the digital signal processor and motor/coil drive IC
62
MICK
O
Serial data transfer clock signal output to the MP3 decoder
63
LCD_CE
O
Latch signal output to the LCD driver
64
MIDIO
I/O
Serial data input/output to/form the MP3 decoder
65
MP3REQ
O
Request signal output to the MP3 decoder
66
MILP
O
Latch pulse signal output to the MP3 decoder
67
ELV_E2
I
ELV_E2 switch signal input from the CD mechanism
68
ELV_E3
I
ELV_E3 switch signal input from the CD mechanism
69
ELV_E1
I
ELV_E1 switch signal input from the CD mechanism
70
SLD_E3
I
SLD_E3 switch signal input from the CD mechanism
71
BVSS
—
Ground terminal
72
BVDD
—
Power supply terminal
73
SLD_E1
I
SLD_E1 switch signal input from the CD mechanism
74
SW5-B
I
SW4 switch signal input from the CD mechanism
75
ELV_POS
O
Elevator motor control signal output for the CD mechanism
76
SLD_POS
O
Loading motor control signal output for the CD mechanism
77
LOD_POS
O
Sled motor control signal output for the CD mechanism
78
SW4
I
SW5-B switch signal input from the CD mechanism
79
SW2-A
I
SW2-A switch signal input from the CD mechanism
80
SW3
I
SW3 switch signal input from the CD mechanism
81
D_SENSOR
I
Disc sensor signal input from the CD mechanism
82
SW1-A
I
SW1-A switch signal input from the CD mechanism
83
SW2-B
I
SW2-B switch signal input from the CD mechanism
84
SW5-A
I
SW5-A switch signal input from the CD mechanism
85
LOD_NEG
O
Sled motor control signal output for the CD mechanism
86
SLD_NEG
O
Loading motor control signal output for the CD mechanism
87
ELV_NEG
O
Elevator motor control signal output for the CD mechanism
88
SLD_E0
I
SLD_E0 switch signal input from the CD mechanism
89
SLD_E2
I
SLD_E2 switch signal input from the CD mechanism
90
ELV_E0
I
ELV_E0 switch signal input from the CD mechanism
91
RE_TRE
I
Jog dial pulse input from the rotary encoder (TREBLE/MIDDLE)
67
CX-BK2
Pin No.
Pin Name
I/O
Description
92
RE_BAS
I
Jog dial pulse input from the rotary encoder (BASS)
93
RE_VOL
I
Jog dial pulse input from the rotary encoder (VOLUME)
94
RE_JOG
I
Jog dial pulse input from the rotary encoder (MULTIJOG)
95
KEY3
I
Key input terminal (A/D input)
96
KEY2
I
Key input terminal (A/D input)
97
KEY1
I
Key input terminal (A/D input)
98
POWER_MONI
I
Voltage detection signal input terminal
99
LEVEL
I
Level mater signal input terminal
100
SUFIX
I
Destination setting input terminal
68
CX-BK2
•
USB AUX BOARD IC700 uAC3553B (USB INTERFACE)
Pin No.
Pin Name
I/O
Description
1
XTI
I
System clock input terminal (12MHz)
2
XTO
O
System clock output terminal (12MHz)
3
AREG1
I
Connected to the external capacitor
4
AVSS_12
—
Ground terminal
5
OUTL
O
USB audio signal output terminal (L-ch)
6
OUTR
O
USB audio signal output terminal (R-ch)
7
AREG0
I
Connected to the external capacitor
8
AVDD
—
Power supply terminal (+5V)
9
DAI
I
Not used
10
WSI
I
Not used
11
CLI
I
Not used
12
INT_DATA
O
Interrupt request signal output to the USB interface IC
13
ACK
O
Acknowledge signal output to the USB interface IC
14 to 19
NC
—
Not used
20
SDA
I/O
I2C data input/output with the system controller
21
SCL
I/O
I2C clock signal input/output to the system controller
22
TRDY
I
Not used
23
VREG
I
Connected to the external capacitor
24
VBUS
I
USB connect detection signal input terminal
25
D–
I
USB data (–) input terminal
26
D+
I
USB data (+) input terminal
27
VSS
—
Ground terminal
28
VDD
—
Power supply terminal (+5V)
29
TEST
I
For test terminal
30
REST
I
Not used
31
SUSPEND
I
Not used
32
SOF
I
Not used
33
SEN
I
Not used
34
FOUTL
O
USB audio signal output terminal (L-ch)
35
FOPL
I
Not used
36
FINL
O
USB audio signal input terminal (L-ch)
37
FOUTR
O
USB audio signal output terminal (R-ch)
38
FOPR
I
Not used
39
FINR
O
USB audio signal input terminal (R-ch)
40, 41
NC
—
Not used
42
SGND
—
Ground terminal
43
SREF
I
Not used
44
NC
I
Not used
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