Sony BMZ-K2 / CX-BK2 Service Manual ▷ View online
61
CX-BK2
– CONNECTOR Board –
IC701, 711, 721
BA6956AN
1
2
3
4
5
6
7
8
9
CONTROL LOGIC
TSD
VREF
O
UT2
O
UT1
RNF
VM
VCC
FIN
GND
RIN
– MAIN Board –
IC501
BU4052BCF-E2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
2X0
X2
VDD
X1
XCOM
X0
X3
A
B
VSS
VEE
INH
2X1
2X3
2XCOM
2X2
IC601
M61529FP-D60G
1
REF
2
MIC
3
INA1
REF
EXTERNAL
INPUT ATT
INPUT ATT
INPUT
ATT
4
INB1
5
INC1
6
IND1
7
RECA1/INEX1
8
RECB1
9
TMI1
10
TMO1
11
TCA1
12
TCB1
13
TCC1
14
TOUT1
16
BB A1
17
BB B1
15
VOLIN1
VOCAL
CUT
TONE ATT
+
TONE CONTROL
(BASS/MID/TREBLE)
ELECTRICAL
VOLUME
18
OUT1
19
SAOUT
20
VCC
BASS
BOOST
21
DATA
MCU
INTERFACE
42
SUR1/DPL1
41
SUR2/DPL2
40
INA2
INPUT
ATT
39
INB2
38
INC2
37
IND2
36
RECA1/INEX2
35
RECB2
34
TMI2
33
TMO2
32
TCA2
31
TCB2
30
TCC2
29
TOUT2
27
BB A2
26
BB B2
28
VOLIN2
+
TONE ATT
TONE CONTROL
(BASS/MID/TREBLE)
ELECTRICAL
VOLUME
25
OUT2
24
SWOUT
23
GND
BASS
BOOST
22
CLOCK
+
SURROUND
OR
DPL BUFFER
+
62
CX-BK2
IC603
NJM2156M (TE2)
BBE
BIAS
MACH3
19 18
HOUTB
HINB
20
INB
17 16
LOUTB
LINB
13
GIN
12
GOUT
11
GND
+
+
15
OUTB
BBE
2
3
HOUTA
HINA
1
INA
4
5
LOUTA
LINA
8
LPOUT
9
LPIN
10
V+
+
6
OUTA
7
BBE
14
VREF
IC905
MM1614A
2
5
VIN
4
VOUT
GND
1
CONT
3
NOISE
DRIVER
THERMAL
SHUTDOWN
BIAS
REFERENCE
+
–
CURRENT
LIMITTER
LIMITTER
63
CX-BK2
7-32.
IC PIN FUNCTION DESCRIPTION
•
BD BOARD IC101 CXD3068Q (DIGITAL SERVO, DIGITAL SERVO PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
DVDD0
—
Power supply terminal (+3.3V) (digital system)
2
XRST
I
Reset signal input from the system controller “L”: reset
3
MUTE
I
Muting on/off control signal input terminal “H”: muting on Not used
4
DATA
I
Serial data input from the system controller
5
XLAT
I
Serial data latch pulse signal input from the system controller
6
CLOK
I
Serial data transfer clock signal input from the system controller
7
SENS
O
Internal status (SENSE) signal output to the system controller
8
SCLK
I
SENSE serial data reading clock signal input from the system controller
9
ATSK
I/O
Input/output terminal for anti-shock Not used
10
WFCK
O
Write frame clock signal output terminal Not used
11
RFCK
O
RFCK signal output terminal Not used
12
XPCK
O
XPCK signal output terminal Not used
13
GFS
O
Guard frame sync signal output terminal Not used
14
C2PO
O
C2 pointer signal output terminal Not used
15
SCOR
O
Subcode sync (S0+S1) detection signal output to the system controller
16
C4M
O
4.2336 MHz clock signal output terminal Not used
17
WDCK
O
Guard subcode sync (S0+S1) detection signal output terminal Not used
18
DVSS0
—
Ground terminal (digital system)
19
COUT
O
Numbers of track counted signal output terminal Not used
20
MIRR
O
Mirror signal output terminal Not used
21
DFCT
I/O
Defect signal input/output terminal Not used
22
FOK
O
Focus OK signal output terminal Not used
23
PWMI
I
Spindle motor external control signal input terminal Not used
24
LOCK
O
GFS is sampled by 460 Hz “H” output when GFS is “H” Not used
25
MDP
O
Spindle motor servo drive signal output to the motor/coil drive IC
26
SSTP
I
Detection signal input from limit in switch The optical pick-up is inner position when “H”
27
FSTO
O
2/3 divider output terminal Not used
28
DVDD1
—
Power supply terminal (+3.3V) (digital system)
29
SFDR
O
Sled servo drive PWM signal (+) output terminal
30
SRDR
O
Sled servo drive PWM signal (–) output terminal
31
TFDR
O
Tracking servo drive PWM signal (+) output terminal
32
TRDR
O
Tracking servo drive PWM signal (–) output terminal
33
FFDR
O
Focus servo drive PWM signal (+) output terminal
34
FRDR
O
Focus servo drive PWM signal (–) output terminal
35
DVSS1
—
Ground terminal (digital system)
36
TEST
I
Input terminal for the test
37
TES1
I
Input terminal for the test
38
VC
I
Middle point voltage (+1.65V) input terminal
39
FE
I
Focus error signal input from the RF amplifier
40
SE
I
Sled error signal input from the RF amplifier
41
TE
I
Tracking error signal input from the RF amplifier
42
CE
I
Middle point servo analog signal input
43
RFDC
I
RF signal input from the RF amplifier
44
ADIO
O
Output terminal for the test Not used
45
AVSS0
—
Ground terminal (analog system)
64
CX-BK2
Pin No.
Pin Name
I/O
Description
46
IGEN
I
Stabilized current input for operational amplifiers
47
AVDD0
—
Power supply terminal (+3.3V) (analog system)
48
ASYO
O
EFM full-swing output terminal
49
ASYI
I
Asymmetry comparator voltage input terminal
50
RFAC
I
EFM signal input from the RF amplifier
51
AVSS1
—
Ground terminal (analog system)
52
CLTV
I
Internal VCO control voltage input terminal
53
FILO
O
Filter output for master PLL
54
FILI
I
Filter input for master PLL
55
PCO
O
Charge pump output for master PLL
56
AVDD1
—
Power supply terminal (+3.3V) (analog system)
57
BIAS
I
Asymmetry circuit constant current input terminal
58
VCTL
I
VCO control voltage input terminal for the wideband EFM PLL Not used
59
V16M
O
VCO oscillation output terminal for the wideband EFM PLL Not used
60
VPCO
O
Charge pump output terminal for the wideband EFM PLL Not used
61
DVDD2
—
Power supply terminal (+3.3V) (digital system)
62
ASYE
I
Asymmetry circuit on/off control signal input terminal “L”: off, “H”: on Not used
63
MD2
I
Digital out on/off control signal input terminal
“L”: digital out off, “H”: digital out on Fixed at “H” in this set
“L”: digital out off, “H”: digital out on Fixed at “H” in this set
64
DOUT
O
Digital audio signal output terminal
65
LRCK
O
L/R sampling clock signal (44.1 kHz) output to the MP3 decoder
66
PCMD
O
Serial data output to the MP3 decoder
67
BCLK
O
Bit clock signal (2.8224 MHz) output to the MP3 decoder
68
EMPH
O
“L” is output when playback disc is emphasis off
“H” is output when playback disc is emphasis on Not used
“H” is output when playback disc is emphasis on Not used
69
XTSL
I
Input terminal for the system clock frequency setting
“L”: 16.9344 MHz, “H”: 33.8688MHz Fixed at “H” in this set
“L”: 16.9344 MHz, “H”: 33.8688MHz Fixed at “H” in this set
70
DVSS2
—
Ground terminal (digital system)
71
XTAI
I
System clock input terminal (33.8688 MHz)
72
XTAO
O
System clock output terminal (33.8688 MHz) Not used
73
SOUT
O
Serial data output terminal Not used
74
SOCK
O
Serial data reading clock signal output terminal Not used
75
XOLT
O
Serial data latch pulse signal output terminal Not used
76
SQSO
O
Subcode Q data output to the system controller
77
SQCK
I
Subcode Q data reading clock signal input from the system controller
78
SCSY
I
Input terminal for resynchronism of guard subcode sync (S0+S1) Not used
79
SBSO
O
Subcode serial data output terminal Not used
80
EXCK
I
Subcode serial data reading clock signal input terminal Not used
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