DOWNLOAD Sony BDV-IS1000 / HT-IS100 / SA-WIS100 / SS-IS15 Service Manual ↓ Size: 6.41 MB | Pages: 104 in PDF or view online for FREE

Model
BDV-IS1000 HT-IS100 SA-WIS100 SS-IS15
Pages
104
Size
6.41 MB
Type
PDF
Document
Service Manual
Brand
Device
Audio
File
bdv-is1000-ht-is100-sa-wis100-ss-is15.pdf
Date

Sony BDV-IS1000 / HT-IS100 / SA-WIS100 / SS-IS15 Service Manual ▷ View online

SA-WIS100/SS-IS15
65
Pin No.
Pin Name
I/O
Description
64, 65
DPSOA, DPSOB
O
Audio serial data output to the stream processor and S-AIR connector
66
VDDINT
-
Power supply terminal (+1.2V) (for core)
67
GND
-
Ground terminal
68
VDDINT
-
Power supply terminal (+1.2V) (for core)
69
GND
-
Ground terminal
70, 71
DPSOC, DPSOD
O
Audio serial data output to the stream processor
72
VDDINT
-
Power supply terminal (+1.2V) (for core)
73
VDDEXT
-
Power supply terminal (+3.3V) (for I/O)
74
GND
-
Ground terminal
75
VDDINT
-
Power supply terminal (+1.2V) (for core)
76
GND
-
Ground terminal
77
DPSOA, DPSOB
O
Audio serial data output to the S-AIR connector
78
DPSIA
I
Audio serial data input from the digital audio interface receiver
79
DPSIB
I
Audio serial data input from the A/D converter or HDMI receiver
80 to 82
DPSIC to DPSIE
I
Audio serial data input from the HDMI receiver
83
VDDINT
-
Power supply terminal (+1.2V) (for core)
84, 85
GND
-
Ground terminal
86
DPDVLRCK
O
L/R sampling clock signal output to the stream processor and S-AIR connector
87
DPDVBCK
O
Bit clock signal output to the stream processor and S-AIR connector
88
DPLRCK
I
L/R sampling clock signal input from the digital audio interface receiver or HDMI receiver
89
DPBCK
I
Bit clock signal input from the digital audio interface receiver or HDMI receiver
90
VDDINT
-
Power supply terminal (+1.2V) (for core)
91, 92
GND
-
Ground terminal
93
VDDEXT
-
Power supply terminal (+3.3V) (for I/O)
94
DPFSCK
I
Audio clock signal input from the digital audio interface receiver or HDMI receiver
95
GND
-
Ground terminal
96
VDDINT
-
Power supply terminal (+1.2V) (for core)
97
NONAUDIO*
I
PCM audio data input from the digital audio interface receiver
98
SF_CE*
-
Not used
99
VDDINT
-
Power supply terminal (+1.2V) (for core)
100
GND
-
Ground terminal
101
VDDINT
-
Power supply terminal (+1.2V) (for core)
102
GND
-
Ground terminal
103
VDDINT
-
Power supply terminal (+1.2V) (for core)
104
GND
-
Ground terminal
105
VDDINT
-
Power supply terminal (+1.2V) (for core)
106
GND
-
Ground terminal
107, 108
VDDINT
-
Power supply terminal (+1.2V) (for core)
109
GND
-
Ground terminal
110
VDDINT
-
Power supply terminal (+1.2V) (for core)
111
GND
-
Ground terminal
112
VDDINT
-
Power supply terminal (+1.2V) (for core)
113
GND
-
Ground terminal
114
VDDINT
-
Power supply terminal (+1.2V) (for core)
115
GND
-
Ground terminal
116
VDDEXT
-
Power supply terminal (+3.3V) (for I/O)
117
GND
-
Ground terminal
118
VDDINT
-
Power supply terminal (+1.2V) (for core)
119
GND
-
Ground terminal
120
VDDINT
-
Power supply terminal (+1.2V) (for core)
121
RESET*
I
Reset signal input from the system controller    "L": reset
122
SPIDS*
I
Device selection signal input from the system controller
123
GND
-
Ground terminal
124
VDDINT
-
Power supply terminal (+1.2V) (for core)
125
SPICLK
I
Serial data transfer clock signal input from the system controller
126
MISO
O
Serial data output to the system controller
SA-WIS100/SS-IS15
66
Pin No.
Pin Name
I/O
Description
127
MOSI
I
Serial data input from the system controller
128
GND
-
Ground terminal
129
VDDINT
-
Power supply terminal (+1.2V) (for core)
130
VDDEXT
-
Power supply terminal (+3.3V) (for I/O)
131
AVDD
-
Power supply terminal (+1.2V) (analog system)
132
AVSS
-
Ground terminal (analog system)
133
GND
-
Ground terminal
134
CLKOUT
O
Local clock signal output terminal    Not used
135
EMU*
O
Emulation status signal output terminal    Not used
136
TDO
O
Test data output terminal (for JTAG)    Not used
137
TDI
I
Test data input terminal (for JTAG)    Not used
138
TRST*
I
Test reset signal input terminal (for JTAG)    Not used
139
TCK
I
Test clock signal input terminal (for JTAG)    Not used
140
TMS
I
Test mode selection signal input terminal (for JTAG)    Not used
141
GND
-
Ground terminal
142
CLKIN
I
System clock input terminal (25 MHz)
143
XTAL
O
System clock output terminal (25 MHz)
144
VDDEXT
-
Power supply terminal (+3.3V) (for I/O)
SA-WIS100/SS-IS15
67
MAIN BOARD  IC1002  R5F3640MDFAR (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
DAMP_SCDT/DIR_DIN
O
Serial data output to the digital audio interface receiver and stream processor
2
DAMP_SHIFT/DIR_DIN
O
Serial data transfer clock signal output to the digital audio interface receiver and stream 
processor
3
XCEC_DI
I
CEC serial data input from the HDMI connector
4
SIRCS_IN
I
SIRCS signal input from the remote control receiver
5
DSP_MOSI
O
Serial data output to the DSP
6
DSP_MISO
I
Serial data input from the DSP
7
DSPSPI_CLK
O
Serial data transfer clock signal output to the DSP
8
BYTE
I
External data bus width selection signal input terminal    Fixed at "L" in this set
9
CNVss
I
Processor mode switch input terminal
10
DIR_XSTATE
I
Source clock selection monitor input from the digital audio interface receiver
11
FL_RST
O
Reset signal output to the fl uorescent indicator tube driver    "L": reset
12
RESET
I
System reset signal input from the reset signal generator    "L": reset    
For several hundreds msec. after the power supply rises, "L" is input, then it change to "H"
13
Xout
O
System clock output terminal (5 MHz)
14
Vss
-
Ground terminal
15
Xin
I
System clock input terminal (5 MHz)
16
Vcc1
-
Power supply terminal (+3.3V)
17
NMI
I
Non-maskable interrupt signal input terminal
18
DIR_ZERO
I
Audio serial data input from the digital audio interface receiver
19
DIR_CSFLAG
I
CSFLAG data input from the digital audio interface receiver
20
XDRIVE_OCP(DIAG)
I
Shut down signal input from the power amplifi er
21
FL_CLK
O
Serial data transfer clock signal output to the fl uorescent indicator tube driver
22
CEC_DO
O
CEC serial data output to the HDMI connector
23
P_CONT2
O
Power on/off control signal output terminal    "H": power on
24
FL_D_OUT
O
Serial data output to the fl uorescent indicator tube driver
25
FL_CS
O
Chip select signal output to the fl uorescent indicator tube driver
26
LED3
O
LED drive signal output terminal for key illumination    "H": LED on
27
DIR_ERROR
I
Error signal input from the digital audio interface receiver    "H": error
28
LED2
O
LED drive signal output terminal for HDMI function on indicator    "H": LED on
29
I2C_CLK
I/O
Two-way I2C clock bus terminal    Not used
30
I2C_DATA
I/O
Two-way I2C data bus terminal    Not used
31
TXD
O
Serial data output to the DMPORT connector
32
RXD
I
Serial data input from the DMPORT connector
33
CLK1
O
Power on/off control signal output terminal for S-AIR    "H": power on
34
S-AIR_SRC_MUTE
O
Sampling rate converter muting control signal output terminal
35
HDMI_TXD
O
Serial data output to the HDMI controller
36
HDMI_RXD
I
Serial data input from the HDMI controller
37
HDMI_RST
O
Reset signal output to the HDMI controller    "L": reset
38
HDMI_MUTE
I
HDMI muting request signal input from the HDMI receiver and HDMI controller
39 to 41
P_CONT1, P_CONT4, 
P_CONT3
O
Power on/off control signal output terminal    "H": power on
42
RDS_DATA
I
RDS serial data input from the TUNER (FM/AM) (AEP and UK models only)
43
TUNED
I
Tuned detection signal input from the tuner (FM/AM)    "L": tuned
44
ST_DI
I
Serial data input from the tuner (FM/AM)
45
ST_CLK
O
Serial data transfer clock signal output to the tuner (FM/AM)
46
DC_DET
I
Over load detection signal input terminal    "L": over load detection
47
TX_RS232C
O
Serial data output terminal for RS-232C    Not used
48
RX_RS232C
I
Serial data input terminal for RS-232C    Not used
49
UPCON_RESET
O
Reset signal output to the sync separator    "L": reset
50
S-AIR LED
O
LED drive signal output terminal for S-AIR transmitter insert indicator    "H": LED on
51
ST_DO
O
Serial data output to the tuner (FM/AM)
52
ST_CE
O
Chip enable signal output to the tuner (FM/AM)
53
ROM_SDA
I/O
Two-way data bus with the EEPROM
54
ROM_SCLK
O
Serial clock signal output to the EEPROM
55
UPCON_I2C_DATA
I/O
Two-way I2C data bus with the sync separator
56
UPCON_I2C_CLK
I/O
Two-way I2C clock bus with the sync separator
SA-WIS100/SS-IS15
68
Pin No.
Pin Name
I/O
Description
57
SURR_RESET
O
Reset signal output to the power amplifi er for surround    Not used
58
S-AIR_DET
I
S-AIR transmitter connection detection signal input from the S-AIR connector    
"L": S-AIR transmitter is connected
59
A_CAL_SW
I
Auto calibration microphone connection detection signal input from ECM-AC2 jack    
"H": Auto calibration microphone is connected
60
DIR_HCE
O
Chip enable signal output to digital audio interface receiver
61
DSP_RESET
O
Reset signal output to the DSP    "L": reset
62
Vcc2
-
Power supply terminal (+3.3V)
63
S-AIR RST
O
Reset signal output to the S-AIR connector    "L": reset
64
Vss
-
Ground terminal
65
P_CONT_HDMI
O
Power on/off control signal output terminal for HDMI section    "H": power on
66
LED
O
LED drive signal output terminal for POWER/ACTIVE STANDBY indicator    "H": LED on
67
S-AIR GPIO2
I
Interrupt signal input from the S-AIR connector
68
DSP_INTR
I
Interrupt request signal input from the DSP
69
DIR RST
O
Reset signal output to the digital audio interface receiver    "L": reset
70
PCM_MULTI
O
DSP input data selection signal output terminal    "L": reset
71
DSP SPIDS
O
Device selection signal output to the DSP
72
DAMP_SOFT_MUTE
O
Soft muting on/off control signal output to stream processor    "L": muting on
73
AC_CUT
I
AC cut detection signal input terminal
74
KEY_INT
I
Key wake-up signal input terminal
75
RDS CLK
I
RDS serial data transfer clock signal input from the tuner (FM/AM) 
(AEP and UK models only)
76
DAMP_INIT
O
Reset signal output to the stream processor    "L": reset
77
S-AIR_I2C_SCL
I/O
Two-way I2C clock bus with the S-AIR connector
78
S-AIR_I2C_SDA
I/O
Two-way I2C data bus with the S-AIR connector
79, 80
DAMP_LATCH2, 
DAMP_LATCH3
O
Serial data latch pulse signal output to the stream processor
81
DRIVE_RST(EN)
O
Reset signal output to the power amplifi er    "L": reset
82
DAMP_LATCH1
O
Serial data latch pulse signal output to the stream processor
83 to 85
OVERFLOW1 to 
OVERFLOW3
I
Overfl ow detection signal input from the stream processor
86
DAMP_LATCH4
O
Serial data latch pulse signal output to the stream processor
87
IO_CE
O
Chip enable signal output to the I/O expander
88
IO_RESET
O
Reset signal output to the I/O expander    "L": reset
89
IO_DI
O
Serial data output to the I/O expander
90
IO_CLK
O
Serial data transfer clock signal output to the I/O expander
91
DMPORT_DET
I
Digital media port adapter connection detection signal input terminal    
"L": digital media port adapter is connected
92
DESTINATION
I
Destination setting terminal
93
MODEL
I
Model setting terminal
94, 95
KEY2, KEY1
I
Front key input terminal (A/D input)
96
AVss
-
Ground terminal
97
KEY0
I
Front key input terminal (A/D input)
98
Vref
I
Reference voltage (+3.3V) input terminal
99
AVcc
-
Power supply terminal (+3.3V)
100
DIR_HDOUT
I
Serial data input from the digital audio interface receiver
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