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TU-X1E/RU

7 – 6

1

VCCA

 -

A-side supply voltage (0.9 V to 5.5 V)

2

SCLA

I

serial clock A-side bus

3

SDAA

I/O

serial data A-side bus

4

GND

 -

supply ground (0 V)

5

EN

I

active HIGH repeater enable input

6

SDAB

I/O

serial data B-side bus

7

SCLB

I

serial clock B-side bus

8

VCCB

 -

B-side supply voltage (2.7 V to 5.5 V)

1

VOUT

O

Output Voltage

2

GND

 -

Ground

3

NC

 -

No Connection

4

CE

I

Chip Enable terminal 

5

GND

 -

Ground

6

VDD

 -

Input power source terminal

TU-X1E/RU

7 – 7

Digital Video Output Pins.

16,15,14,13,10,9,

8,7,3,2,1, 

144,141,140,139,
138,135,134,133,
132,129,128,127,
126,123,122,121,

120,117,116,115,
114,111,110,109, 

108

Q0-35

O

36-bit Output Pixel Data Bus.
It supports a wide array of output formats, including multiple RGB and YCbCr bus for-
mats.

19

DE

O

Data enable.

20

HSYNC

O

Horizontal Sync Output control signal.

21

VSYNC

O

Vertical Sync Output control signal.

22

EVNODD

O

indicates Even or Odd Field for interlaced Formats.

5

ODCK

O

Output Data Clock.

Digital Audio Output Pins.

95

XTALIN

I

Crystal Clock Input.

94

XTALOUT

O

Crystal Clock Output.

89

MCLK

O

Audio Master Clock Output.

86

SCK/DCLK

O

I2S Serial Clock Output.
DSD Clock Out.

85

WS/DR0

O

I2S Word Select Output.
DSD Serial Right Ch0 Data Output.

81

SD0/DL0

O

I2S Serial Data Output./DSD Audio Output Configurable to be shared with OSD.
SD0=DSD Serial Left Ch0 Data Output.
SD1=DSD Serial Right Ch1 Data Output.
SD2=DSD Serial Left Ch1 Data Output.
SD3=DSD Serial Right Ch2 Data Output.

82

SD1/DR1

O

83

SD2/DL1

O

84

SD3/DR2

O

78

SPDIF/DL2

O

S/PDIF Audio Output. Configurable to be shared with DSD.
DSD Serial Left Ch2 Data Output.

75

MUTEOUT

O

Mute Audio Output. Signal to the external downstream audio device, audio DAC, etc, 
to mute audio output.

Configuration/Programming Pins.

102

INT

O

Interrupt Output.

100

RESET#

I

Reset Pin. Active LOW.  5V Tolerant.

34

DSCL0

I

DDCI2C Clock for Port 0.  5V Tolerant.

33

DSDA0

I/O

DDCI2C Data for Port 0.  5V Tolerant.

29

DSCL1

I

DDCI2C Clock for Port 1.  5V Tolerant.

28

DSDA1

I/O

DDCI2C Data for Port 1.  5V Tolerant.

27

CSCL

I

Configuration/Status I2C Clock.  5V Tolerant.

26

CSDA

I/O

Configuration/Status I2C Data.  5V Tolerant.

105

CI2CA

I

Local I2C Adress Select. 5V Tolerant.

101

SCDT

O

Indicates active video at HDMI input  port.

35

R0PWR5V

I

Port 0 Transmitter Detect. 5V Tolerant.

30

R1PWR5V

I

Port 1 Transmitter Detect. 5V Tolerant.

98,77,76,55

RSVDNC

 -

Reserved, must be unconnected.

99

RSVDL

I

Reserved, must be tied to ground.

Differential Signal Data Pins.

40

R0XC+

I

TMDS input clock pair.  HDMI Port 0.

39

R0XC-

I

44

R0X0+

I

TMDS input data pair.   HDMI Port 0.

43

R0X0-

I

48

R0X1+

I

TMDS input data pair.   HDMI Port 0.

47

R0X1-

I

52

R0X2+

I

TMDS input data pair.   HDMI Port 0.

51

R0X2-

I

58

R1XC+

I

TMDS input clock pair.  HDMI Port 1.

57

R1XC-

I

62

R1X0+

I

TMDS input data pair.   HDMI Port 1.

61

R1X0-

I

66

R1X1+

I

TMDS input data pair.   HDMI Port 1.

65

R1X1-

I

70

R1X2+

I

TMDS input data pair.   HDMI Port 1.

69

R1X2-

I

TU-X1E/RU

7 – 8

Power and Ground Pins.
12, 24, 25, 80, 91, 

107, 119, 131, 

143

CVCC18

---

Digital Logic VCC  1.8V

11, 23, 79, 90, 
106, 118, 130, 

142, 

CGND

---

Digital Logic ground..

6, 18, 32, 74, 88, 

104, 113, 125, 

137, 

IOVCC33

---

Input/Output Pin Supply.  3.3V

4, 17, 31, 73, 87, 

103, 112, 124, 

136, 

IOGND

---

Input/Output Pin ground.

38, 42, 46, 50, 56, 

60, 64, 68, 

AVCC33

---

TMDS Analog VCC.  3.3V

36, 41, 45, 49, 53, 

59, 63, 67, 71 

AGND

---

TMDS Analog ground.

37,54,72

AVCC18

---

TMDS Analog VCC  1.8V.

92

DVCC18

---

audio clock regeneration PLL analog VCC.  1.8V

93

DGND

---

audio clock regeneration PLL  analog ground.

96

XTALVCC

---

audio clock regeneration PLL crystal oscillator power.  3.3V

97

REGVCC

---

audio clock regeneration PLL crystal oscillator power.  3.3V

TU-X1E/RU

7 – 9

Digital Video Input Pins.

98,97,96,95,94,9

3,92,91,90,86,85,

84,

D[0:11]

I

These are the lower 12bits of the 36-bit pixel bus.
These pins are highly configrable, and support multiple RGB and YCbCr format.

83,82,81,80,79,7

8,77,75,74,73,72,

71,

D[12:23]

I

These are the middle 12 bits of the 36-bit pixel bus. 

70,69,68,67,63,6

2,61,60,59,58,57,

56

D[24:35]

I

These are the upper 12 bits of the 36-bit pixel bus.

88

IDCK

I

Input Data Clock.

1

DE

I

Data enable.

2

HSYNC

I

Horizontal Sync Input control signal.

3

VSYNC

I

Vertical Sync Input control signal.

Digital Audio Output Pins.

11

SCK

I

I2S Serial Clock Input.

10

WS

I

I2S Word Select Input.

9

SD0

I

I2S Serial Data Input. 0

8

SD1

I

I2S Serial Data Input. 1

7

SD2

I

I2S Serial Data Input. 2

6

SD3

I

I2S Serial Data Input. 3

23,21,19,17

DL[3:0]

I

One-bit Audio Data Left [3:0]

22,20,18,16

DR[3:0}

I

One-bit Audio Data Right [3:0]

15

DCLK

I

One-bit Audio Clock Input.

5

MCLK

I

Audio Input Master Clock.

4

SPDIF

I

S/PDIF Audio Input. 

Configuration/Programming Pins.

51

HPD

I

Hot Plug Detect Input

52

RSVDL

I

Reserved for use by Sillicon Image and must be tied LOW.

24

INT

O

Interrupt Output.

Control Pins.

50

CI2CA

I

I2C Device Adress Select. 5V Tolerant.

25

RESET#

I

Reset Pin. Active LOW.  5V Tolerant.

48

CSCL

I

Configuration/Status I2C Clock. 

49

CSDA

I/O

Configuration/Status I2C Data. (Open drain output) 

46

DSCL

I

DDC I2C Clock . (Open drain output) 

47

DSDA

I/O

DDC I2C Data .  (Open drain output) 

Differential Signal Data Pins.

34

TX0+

O

TMDS output data pair.  

33

TX0-

O

37

TX1+

O

TMDS output data pair. 

36

TX1-

O

40

TX2+

O

TMDS output data pair. 

39

TX2-

O

31

TXC+

O

TMDS output clock pair. 

30

TXC-

O

27

EXT_SWING

I

Voltage swing adjust. A resister is tied from this pin to AVCC. This rester determines 
the amplitude of the voltage swing. Recommend 698

Ω 1% when source termination 

and leakage bias is on and 845

Ω 1% when source termination and leakage bias is off.

Power and Ground Pins.

12,55,64,76,99

CVCC18

---

Digital Logic core VCC. 1.8V

14,53,66,89

IOVCC33

---

Input/Output pin VCC .  3.3V

44

AVCC33

---

Analog VCC. 3.3V

32,38

AVCC18

---

Analog VCC.  1.8V.

26,29,35,41,43

AGND

---

Analog ground.

28

PVCC1

---

TMDS core PLL power. 1.8V

42

PVCC2

---

Filter PLL power. 1.8V

45

DDCPWR5V

---

Power reference signal.  Used to supply power to the DDC I2C pads when chip is 
powered off. 5V

13,54,65,87,100

GND

---

Digital ground..