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TU-X1E/RU

7 – 13

1

BOOT

I

HS Driver Supply.
Connect through a capacitor (100nF) to the floating node (LS-Drain) pin
and provide necessary bootstrap diode from VCC.

2

UGATE

-

HS Driver Output. Connect to HS mosfet gate.

3

GND

I

All internal references, logic and drivers are connected to this pin.
Connect to the PCB ground plane.

4

LGATE/OC

I

LGATE. LS Driver Output. Connect to LS mosfet gate.
OC. Over Current threshold set. During a short period of time following
VCC rising over UVLO threshold, a 10

µA current is sourced from this pin.

Connect to GND with an ROCSET resistor greater than 5k

Ω to program OC 

Threshold. The resulting voltage at this pin is sampled and held internally as the 
OC set point. Maximum programmable OC threshold is 0.55V. 
A voltage greater than 0.75V (max) activates an internal clamp and causes
OC threshold to be set at 400 mV. 
ROCSET not connected sets the 400mV default threshold.

5

VCC

-

Device and LS Driver power supply.
Operative range from 4.1V to 13.2V. Filter with at least 1

µF MLCC to GND.

6

FB

I

Error Amplifier Inverting Input.
Connect with a resistor RFB to the output regulated voltage. Additional
resistor ROS to GND may be used to regulate voltages higher than the reference.

7

COMP/DIS

 

I

COMP. Error Amplifier Output. Connect with an RF - CF // CP to GND to
compensate the device control loop in conjunction to the FB pin.
During the Soft-Start phase, a 10

µA current is sourced from this pin so the

compensation capacitors also act to program the SS time.
DIS. The device can be disabled by pulling this pin lower than 0.4V (min).
Setting free the pin, the device enables again.

8

PHASE

I

HS Driver return path, current-reading and adaptive-dead-time monitor.   
Connect to the LS drain to sense RdsON drop to measure the output current.  
This pin is also used by the adaptive-dead-time control circuitry to monitor   
when HS mosfet is OFF.   

1

BS

I

High-Side gate drive boost input. BS supplies the drive for the high-side N-Channel 
MOSFET switch. Connect a 0.01

µF or greater capacitor from SW to BS to power the 

high-side switch.

2

IN

 

-

Power input. IN supplies the power to the IC, as well as the step-down converter 
switches. Drive IN with a 4.75V to 28V power source. Bypass IN to GND with a suit-
ably large capacitor to eliminate noise on the input to the IC. 

3

SW

O

Power switching output. SW is the switching node that supplies power to the output. 
Connect the output LC filter from SW to the output load. Note that a capacitor is 
required from SW to BS to power the high-side switch.

4

GND

 -

Ground

5

FB

I

Feedback input. FB senses the output voltage to regulate that voltage. Drive FB with a 
resistive voltage driver from the output voltage. The feedback reference voltage is 
0.795V. 

6

FB

I

Compensation Node. COMP is used to compensate the regulation control loop. Con-
nect a series RC network from COMP to GND to compensate the regulation control 
loop. In side cases, an additional capacitor from COMP to GND is required.

7

EN

I

Enable Input. EN is a digital input that turns the regulator on or off. Drive EN higher 
than 2.7V to turn on the regulator, drive it lower than 1.1V to turn it off . Pull up with 
100K resister for automatic startup.

8

SS

I

Soft-start control input. SS control the soft-start period. Connect a capacitor from SS 
to GND to set the soft-start period. 

TU-X1E/RU

7 – 14

45,46

CK, CK

I

Clock: CK and CK# are differential clock inputs. 
All adress and control input signals are sampled on the positive edge of CK and nega-
tive edge of CK#. 
Output (read) data is referenced to the both edges of CK. Internal clock signals are 
derived from CK/CK#

44

CKE

I

Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, 
and device input buffers and output drivers. 
Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all 
banks idle), or Active Power-Down (row Active in any bank). 
CKE is synchronous for power down entry and exit, and for self refresh entry. 
CKE is asynchronous for self refresh exit, and and for output disable. 
CKE must be maintained high throughout Read and Write accesses. 
Input buffers, excluding CK, CK# and CKE are disabled during Power-Down. 
Input buffers, excluding CKE, are disabled during Self Refresh.

24

CS

I

Chip Select: CS# enables (resistered LOW) and disables (resistered HIGH) the com-
mand decoder. 
All commands are masked when CS# is resisters HIGH. 
CS# provides for external bank selection on system with multiple banks. 
CS# is considered part of the command code.

23,22,21

RAS, CAS, WE

I

Command Inputs: RAS, CAS and WE (along with CS) define the command being 
entered.

20, 49

LDM,UDM

I

Input Data Mask: DM is an input mask signal for write data. 
Input data is masked when DM is sampled HIGH along with that input data during a 
WRITE access. 
DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ and DQS loading.

26, 27

BA0 - BA1

I

Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE 
or PRECHARGE command is being applied. 

28, 29, 30, 31, 
32, 35, 36, 37, 

38, 39, 40, 41, 42

A [0:12]

I

Address Inputs: Provided the row address for ACTIVE commands, and the column 
address and AUTO PRECHARGE bit for READ/WRITE commands, to select one 
location out of the memory array in the respective bank. 
A10 is sampled during a PRECHARGE command to determine whether the PRE-
CHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). 
If only one bank is to be precharged, the bank is selected by BA0, BA1. 
The address inputs also provide the op-code during MODE REGISTER SET com-
mands.
BA0 and BA1 define which mode register is loaded during the MODE RESISTER SET 
command (MRS or EMRS).

2, 4, 5, 7, 8, 10, 

11, 13, 54, 56, 57, 

59, 60, 62, 63, 65

DQ

I/O

Data Input/ Output:  Data bus.

16,

51

LDQS,

UDQS,

I/O

Data Strobe: output with read data, input with write data. Edge-aligned with read data, 
centered in write data. Used to capture write data. 
For the *16, LDQS corresponds to the data on DQ0-DQ7; UDQS corresponds to the 
data on DQ8-DQ15. 
LDQS is NC on *4 and *8.

14, 17, 19, 25, 

43, 50, 53

NC

 -

No Connect: No internal electrical connection is present.

3, 9, 15, 55, 61

VDDQ

 -

DQ Power Supply: 2.5V 

± 0.2V.

6, 12, 52, 58, 64

VSSQ

 -

DQ Ground.

1, 18, 33

VDD

 -

Power Supply: 2.5V 

± 0.2V.

34,48,66

VSS

 -

Ground.

49

VREF

 -

SSTL_2 reference voltage.

TU-X1E/RU

7 – 15

48,25,24-

16,13,10-1

A21-A0

I

22 Address inputs

44-36,36-29

DQ14-DQ0

I/O

15 Data Inputs/Outputs.   

45

DQ15A-1
(or DQ15)

I/O

Data input/output or Address input 
(or data input/output)

26

E#

I

Chip Enable input.  

28

G#

I

Output Enable input.

11

W#

I

Write Enable input.  

12

RP#

I

Reset/Block Temporary Unprotect

17

R/B#

O

Ready/Busy Output

47

BYTE#

I

Byte/Word Organization Select

37

VCC

-

Supply Voltage

14

VPP/WP#

I

Supply Voltage for fast program (optional) or Write Protect

27,46

VSS

-

Ground

NC

-

Not Connected Internally.    

TU-X1E/RU

7 – 16

1

S1_1

I

S Terminal discrimination connection detection

7

S1_2

I

 The discrimination result is outputted to a Status register.

13

S1_3

I

19

S1_4

I

2

Y1

I

Luminance signal input Y1

8

Y2

I

Luminance signal input Y2

14

Y3

I

Luminance signal input Y3

20

Y4

I

Luminance signal input Y4

3

S2_1/FS1

I

S Terminal discrimination aspect ratio information input or SCART terminal FS discrimination

9

S2_2/FS2

I

 When using it as FS discrimination, it attenats by the resistance division of 47K+33K. 

15

S2_3/FS3

I

21

S2_4/FS4

I

4

C1

I

Chroma signal input C1

10

C2

I

Chroma signal input C2

16

C3

I

Chroma signal input C3

22

C4

I

Chroma signal input C4

5

O1

I

General-purpose output

17

O2

I

 It is an open collector type general-purpose output port of the I2C control.

23

O3

I

29

O4

I

6

V2

I

Composite signal input V2

12

V3

I

Composite signal input V3

18

V4

I

Composite signal input V4

24

V5

I

Composite signal input V5

26

V6

I

Composite signal input V6

28

V7

I

Composite signal input V7

100

V1

I

Composite signal input V1

33

VCC9

-

Power-supply voltage 9V

61
72
27

VCC5

-

Power-supply voltage 9V

66
99
25

GND

-

Ground

30
40
64
68
80

11

BIAS

 -

Bias
 All the reference voltages used in IC are made based on the resistance division of this terminal. 
 It is a terminal that puts up the filter capacitor outside for the reference voltage stabilization. 

76

ADR

I

Slave address setting
 Slave address 90H and 92H can be selected according to the voltage applied to this terminal. 
 It is set to 90H by Low, and is set to 92H by High.

31

SCL

I

I2C BUS clock input

32

SDA

I/O

I2C BUS data input/output

41-60

L1-L10
R1-R10

I

Audio line input
 It equips it with ten systems. 

34-39

LOUT1-3
ROUT1-3

O

Audio line output
 0dB/6dB of the voltage gain is selected by the control register. 

62

DCOUT

O

DC output terminal for S terminal

65

VOUT3

O

Monitor output terminal (composite)

63

COUT3/
VOUT6

O

Monitor output terminal (Chroma or composite)

67

VOUT3/
VOUT5

O

Monitor output terminal (Luminance or composite)

69

PROUT2

O

Color difference Pr signal output terminal 2

70

PBOUT2/
COUT2

O

Color difference Pb signal output terminal 2