DOWNLOAD Sharp PZ-43MR2E (serv.man8) Service Manual ↓ Size: 531.78 KB | Pages: 23 in PDF or view online for FREE

Model
PZ-43MR2E (serv.man8)
Pages
23
Size
531.78 KB
Type
PDF
Document
Service Manual
Brand
Device
TV / LCD / Description of major functions
File
pz-43mr2e-sm8.pdf
Date

Sharp PZ-43MR2E (serv.man8) Service Manual ▷ View online

32
PZ-43MR2E
PZ-50MR2E
Ë
VHICXA2101Q-1 (ASSY: IC803)
»
Baseband Video Signal Processor
»
Block Diagram
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Pin Function
Pin No.
Pin Name
I/O
Pin Function
IN2-H
IN2-V
IN2-1
IN2-2
IN2-3
Vcc-MAT
IN3-H
IN3-V
IN3-1
IN3-2
IN3-3
GND-MAT
IN4-H
IN4-V
IN4-1
IN4-2
IN4-3
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IN2-H : Independent horizontal sync signal input terminal.
IN2-V : Independent vertical sync signal input terminal.
IN2 line signal input terminal.
Selector line and sync processor line power terminal.
IN3-H : Independent horizontal sync signal input terminal.
IN3-V : Independent vertical sync signal input terminal.
IN3 line signal input terminal.
Selector line and sync processor line grounding terminal.
IN4-H : Independent horizontal sync signal input terminal.
IN4-V : Independent vertical sync signal input terminal.
IN4 line signal input terminal.
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PZ-43MR2E
PZ-50MR2E
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Pin Function
Pin No.
Pin Name
I/O
Pin Function
V-PH
IN5-H
IN5-V
IN5-1
IN5-2
IN5-3
H-PH
YG-OUT
YG-IN
IREF-SYNC
VS-OUT
HS-OUT
Vcc-OUT
SCP-IN
VTIM-IN
HP-IN
GND-OUT
R-OUT
G-OUT
B-OUT
R-SH
G-SH
B-SH
IK-IN
PABL-FIL
ABL-FIL
ABL-IN
YS/YM-1
LR1-IN
LG1-IN
LB1-IN
YS/YM-2
LR2-IN
LG2-IN
LB2-IN
ADDRESS
DPIC-C
SCL
SDA
DPIC-MUTE
CLP-C
VM-OUT
VM/SHP/COL-OFF
YCBCR-SW
ECR-IN
ECB-IN
EY-IN
V1-IN
H1-IN
CR1-IN
CB1-IN
Y1-IN
GND-SIG
IREF-YC
Vcc-SIG
SELCR-IN
SELCB-IN
SELY-IN
SELY-OUT
SELCB-OUT
SELCR-OUT
SELH-OUT
SELV-OUT
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O
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O
O
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O
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O
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Vsync peak holding capacitor connection terminal.
IN5-H : Independent horizontal sync signal input terminal.
IN5-V : Independent vertical sync signal input terminal.
IN5 line signal input terminal.
Hsync peak holding capacitor connection terminal.
Sync separation composite video signal output terminal.
Sync separation composite video signal input terminal.
Reference current setting terminal (about 4.6V)
Used to select between IN1-line HV and IN2/IN5-line selector output HV by I2C BUS
“YCBCR/MAT” and feed out the signal in positive polarity.
RGB line power terminal.
Sand-Castle-Pulse input terminal.
V timing pulse input terminal.
H pulse input terminal.
RGB line grounding terminal.
RGB signal output terminal.
Output to be made at 2.6Vp-p with 100IRE white input.
RGB AKB sample-and-hold terminal.
Reference pulse to return to this terminal.
Peak ABL peak holding terminal.
Used to form LPF for ABL control signal.
ABL control signal input terminal.
YM1/YS1 control input terminal. Input level to be of 3 values.
VM turning-off function also available when YM and YS have reached their specified values.
Analog RGB1 signal input terminal.
YM2/YS2 control input terminal. Input level to be of 3 values.
VM turning-off function also available when YM and YS have reached their specified values.
Analog RGB2 signal input terminal.
I2C BUS slave address setting terminal.
Capacitor to be connected for grounding in order to detect the black signal in dynamic
picture (black stretching).
I2C BUS standard SCL (Serial Clock) input terminal.
I2C BUS standard SDA (Serial Data) input terminal.
Used to control MUTE of dynamic picture (black stretching).
Y line clamp capacitor connection terminal.
VM output terminal to feed out Y signal’s differential waveform in positive polarity.
Used to turn off VMÅASHARPNESS and COLOUR. Input level to be 3 values
Used to switch between INT and EXT SW input signals. External input terminal to be
selected at High level.
External Y, Cb, and Cr input terminals.
IN1-line HV input terminal. Positive-polarity input.
IN1-line Y, Cb, and Cr input terminals.
Y color difference signal processor grounding terminal.
Reference current setting terminal (mainly for Y color difference signal processing line).
Y color difference signal processor power terminal.
Used to feed in selector outputs Y, Cb, and Cr through clamp capacitor.
IN2- thru IN5-line selector output terminals.
Used to feed out Y-, Cb-, and Cr-converted signals.
IN2 thru IN5 selector HV output terminals.
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PZ-43MR2E
PZ-50MR2E
Ë
RH-iX3566CEZZ (ASSY: IC1901)
»
PLD (Programmable Logic Device)
»
Pin Function
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Pin No.
Pin Name
I/O
Pin Function
TDI
VD1
SP_HD
GND
SP_VD
SP_CP
TMS
HD3
VCC
VD3
GND
MODEA
MODEB
MODEC
SELA
GND
VCC
SELO
HD2
VD2
HDS
VDS
US_VD
GND
US_HD
TCK
TEXT_VD
TEXT_HD
VCC
GND
PL_BLK
TDO
PLCP
PL_HD
PL_VD
GND
GCLK1
OE1
GCLRn
OE2/GCLK2
VCC
CNR_CP
CNR_HBLK
HD1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

I/O
I/O
I/O
I/O
I/O
I
I
I
I
I/O
I/O
I/O
Ground
Power supply (3.3V)
Ground
Ground
Power supply (3.3V)
Ground
Power supply (3.3V)
Ground
Ground
External clock input. 16MHz
Power supply (3.3V)
35
PZ-43MR2E
PZ-50MR2E
Ë
VHiTA1318AF-1 (ASSY: IC604)
»
Sync Processor
»
Block Diagram
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