DOWNLOAD Sharp LC-46X8E Service Manual ↓ Size: 9.84 MB | Pages: 29 in PDF or view online for FREE

Model
LC-46X8E
Pages
29
Size
9.84 MB
Type
PDF
Document
Service Manual
Brand
Device
TV / LCD / Major IC Informations
File
lc-46x8e.pdf
Date
PREV: Sharp LC-46X20E (serv.man23) Service Manual / Technical Bulletin

Sharp LC-46X8E Service Manual ▷ View online

LC-46X8E/S/RU
5 – 13
AP8
TCLK1P
O
LVDS Positive clock Output. (no connected)
open
AN8
TCLK1M
O
LVDS Negative clock Output. (no connected)
open
AP9
TC1P
O
LVDS Positive Output. (no connected)
open
AN9
TC1M
O
LVDS Negative Output. (no connected)
open
AJ4
LVDS_VDDO
—
LVDS Output buffer VDD (+3.3V).
D3.3V
AP10
TB1P
O
LVDS Positive Output. (no connected)
open
AN10
TB1M
O
LVDS Negative Output. (no connected)
open
AP11
TA1P
O
LVDS Positive Output. (no connected)
open
AN11
TA1M
O
LVDS Negative Output. (no connected)
open
AL5
LVDS_VSSO
—
LVDS Output buffer VSS.
GND
AM5
LVDS_VDDO
—
LVDS Output buffer VDD (+3.3V).
D3.3V
AL3
LVDS_VSSA
—
LVDS Analog VSS.
GND
AL4
LVDS_VDDA
—
LVDS Analog VDD (+3.3V).
D3.3V
AK3
LVDS_VSSD
—
LVDS Digital VSS.
GND
AM3
LVDS_VDDD
—
LVDS Digital VDD (+3.3V).
D3.3V
PLL Interface
B7
DVSS22
—
PLL ground related to DVDD22; supply for VCO circuit.
GND
A7
DVDD22
—
PLL power= 1.2V; supply for VCO circuit.
R-D1.3V
A6
DVSS21
—
PLL ground related to DVDD21; supply for digital circuit.
GND
B6
DVDD21
—
PLL power= 1.2V; supply for digital circuit.
R-D1.3V
C6
AVSS7
—
PLL ground related to AVDD7.
GND
D6
MCLK2LF
—
Low pass filter for MCLK2PLL.
C-D3.3V
E6
AVDD7
—
PLL analog power= 3.3V; supply for MCLK2PLL.
D3.3V
D5
AVSS6
—
PLL ground related to AVSS6.
GND
C5
MPEGCLK2LF
—
Low pass filter for MPEGCLK2PLL.
C-D3.3V
B5
AVDD6
—
PLL analog power= 3.3V; supply for MPEGCLK2PLL.
D3.3V
A5
AVSS5
—
PLL ground related to AVSS5.
GND
A4
MPEGCLK1LF
—
Low pass filter for MPEGCLK1PLL.
C-D3.3V
B4
AVDD5
—
PLL analog power= 3.3V; supply for MPEGCLK1PLL.
D3.3V
C4
AVSS2
—
PLL ground related to AVSS2.
GND
D4
PLF
—
Low pass filter for PCLKPLL.
C-D3.3V
C3
AVDD2
—
PLL analog power= 3.3V; supply for PCLKPLL.
D3.3V
B3
AVSS1
—
PLL ground related to AVSS1.
GND
A3
MLF
—
Low pass filter for MCLKPLL.
C-D3.3V
A2
AVDD1
—
PLL analog power= 3.3V; supply for MCLKPLL.
D3.3V
B2
AVSS4
—
PLL ground related to AVSS4.
GND
A1
IDELF
—
Low pass filter for IDECLKPLL.
C-D3.3V
B1
AVDD4
—
PLL analog power= 3.3V; supply for IDECLKPLL.
D3.3V
C1
AVDD3
—
PLL analog power= 3.3V; supply for CK48MPLL.
D3.3V
C2
CK48MLF
—
Low pass filter for CK48MPLL.
C-D3.3V
D3
AVSS3
—
PLL ground related to AVSS3.
GND
D2
XTLI
I
24MHz_PLL crystal input.
X-TAL
D1
XTLO
O
24MHz_PLL crystal output.
X-TAL
E1
DVSS12
—
PLL ground related to DVDD12; supply for VCO circuit.
GND
E2
DVDD12
—
PLL power= 1.2V; supply for VCO circuit.
R-D1.3V
E3
DVSS11
—
PLL ground related to DVDD11; supply for digital circuit.
GND
E4
DVDD11
—
PLL power= 1.2V; supply for digital circuit.
R-D1.3V
FLASH Interface
E25
AD30_FRA14
I/O
Flash address 14/PCI AD bus bit 30.
FRA_14
D24
AD28_FRA12
I/O
Flash address 12/PCI AD bus bit 28.
FRA_12
E24
AD26_FRA10
I/O
Flash address 10/PCI AD bus bit 26.
FRA_10
A23
AD29_FRA13
I/O
Flash address 13/PCI AD bus bit 29.
FRA_13
B23
AD31_FRA15
I/O
Flash address 15/PCI AD bus bit 31.
FRA_15
D23
AD24_FRA8
I/O
Flash address 8/PCI AD bus bit 24.
FRA_8
E23
AD22_FRA6
I/O
Flash address 6/PCI AD bus bit 22.
FRA_6
A22
CBE3#_FRA19
I/O
Flash address 19/PCI CBE#[3].
FRA_19
B22
AD25_FRA9
I/O
Flash address 9/PCI AD bus bit 25.
FRA_9
C22
AD27_FRA11
I/O
Flash address 11/PCI AD bus bit 27.
FRA_11
D22
AD20_FRA4
O
Flash address 4/PCI AD bus bit 20/POD host interface Card access 
register selection.
FRA_4
E22
AD18_FRA2
O
Flash address 2/PCI AD bus bit 18/POD host interface Card output 
enable.
FRA_2
A21
AD19_FRA3
O
Flash address 3/PCI AD bus bit 19/POD host interface Card Write 
enable.
FRA_3
B21
AD21_FRA5
O
Flash address 5/PCI AD bus bit 21.
FRA_5
Pin No.
Pin Name
I/O
Pin Function
Sheet Name
LC-46X8E/S/RU
5 – 14
C21
AD23_FRA7
O
Flash address 7/PCI AD bus bit 23.
FRA_7
D21
AD16_FRA0
O
Flash address 0/PCI AD bus bit 16/POD host interface Card output 
enable.
FRA_0
A20
IRDY_PCAS
I/O
PCI bus IRDY# signal/M68K CPU interface address strobe signal.
PCI_IRDY
B20
CBE2#_FRA18
O
Flash address 18/PCI CBE#[2].
FRA_18
C20
AD17_FRA1
O
Flash address 1/PCI AD bus bit 17/POD host interface Card Write 
enable.
FRA_1
A19
CBE1#_FRA17
O
Flash address 17/PCI CBE#[1].
FRA_17
E19
AD15_FRD15
I/O
Flash Data bus bit 15/PCI AD bus bit 15.
FRD_15
A18
AD7_FRD7
I/O
Flash Data bus 7/PCI AD bus bit 7.
FRD_7
B18
AD10_FRD10
I/O
Flash Data bus bit 10/PCI AD bus bit 10/POD host interface address 
bit 2.
FRD_10
C18
AD12_FRD12
I/O
Flash Data bus bit 12/PCI AD bus bit 12/POD host interface address 
bit 10.
FRD_12
D18
AD13_FRD13
I/O
Flash Data bus bit 13/PCI AD bus bit 13/POD host interface address 
bit 13.
FRD_13
E18
AD11_FRD11
I/O
Flash Data bus bit 11/PCI AD bus bit 11/POD host interface address 
bit 3.
FRD_11
A17
AD8_FRD8
I/O
Flash Data bus bit 8/PCI AD bus bit 8/POD host interface address 
bit 0.
FRD_8
B17
AD14_FRD14
I/O
Flash Data bus bit 14/PCI AD bus bit 14/POD host interface address 
bit 12.
FRD_14
C17
AD9_FRD9
I/O
Flash Data bus bit 9/PCI AD bus bit 9/POD host interface address 
bit 1.
FRD_9
D17
AD6_FRD6
I/O
Flash Data bus bit 6/PCI AD bus bit 6/POD host interface Data bus 
bit 6.
FRD_6
E17
CBE0#_FRA16
O
Flash address bit 16/PCI CBE#[0].
FRA_16
A16
AD5_FRD5
O
Flash Data bus bit 5/PCI AD bus bit 5/POD host interface Data bus 
bit 5.
FRD_5
B16
AD1_FRD1
I/O
Flash Data bus bit 1/PCI AD bus bit 1/POD host interface Data bus 
bit 1.
FRD_1
C16
AD3_FRD3
I/O
Flash Data bus bit 3/PCI AD bus bit 3/POD host interface Data bus 
bit 3.
FRD_3
D16
AD2_FRD2
I/O
Flash Data bus bit 2/PCI AD bus bit 2/POD host interface Data bus 
bit 2.
FRD_2
E16
AD4_FRD4
I/O
Flash Data bus bit 4/PCI AD bus bit 4/POD host interface Data bus 
bit 4.
FRD_4
E15
AD0_FRD0
I/O
Flash Data bus bit 0/PCI AD bus bit 0/POD host interface Data bus 
bit 0.
FRD_0
D15
FRA25
I/O
Flash address bit 25.
FRA_25
C15
FRA24
I/O
Flash address bit 24.
FRA_24
B15
FRA23
I/O
Flash address bit 23.
FRA_23
A15
FRA22
I/O
Flash address bit 22.
FRA_22
A14
FRA21
I/O
Flash address bit 21.
FRA_21
B14
FRA20
I/O
Flash address bit 20.
FRA_20
C14
GCS3
I/O
Flash chip select (0: Active).
TL8103
D14
GCS2
I/O
Flash chip select (0: Active).
TL8104
E14
GCS1
I/O
Flash chip select (0: Active).
N_CPLD_CS1
E13
GCS0
I/O
Flash chip select (0: Active).
N_CPLD_CS2
D13
BOOTCS
O
EPPROM chip select (0: Active).
ROM_CE
C13
FWE#
O
Write enable signal of Flash Rom.
XEWE
B13
FOE#
O
Read enable signal of Flash Rom.
XERE
A13
NAND_CE#
O
Chip select signal of NAND Flash Rom.
TL8102
A12
NAND_RDY
I
Ready signal of NAND Flash Rom.
TL8101
PCI Interface
A27
INTA
I
PCI interrupt A.
R-D3.3V
C25
INTB
I
PCI interrupt B.
R-D3.3V
B27
INTC
I
PCI interrupt C.
R-D3.3V
B25
INTD
I
PCI interrupt D.
R-D3.3V
D27
GNT0
O
PCI gnt signal. (no connected)
open
D26
GNT1
O
PCI gnt signal. (no connected)
open
E26
GNT2
O
PCI gnt signal. (no connected)
open
D25
GNT3
O
PCI gnt signal. (no connected)
open
C27
PCIRST#
O
PCIRSTN/68K clock output.
R-D3.3V
A25
PCICLK
O
PCI clock.
R-D3.3V
C24
REQ0
I
PCI req signal.
R-D3.3V
Pin No.
Pin Name
I/O
Pin Function
Sheet Name
LC-46X8E/S/RU
5 – 15
B24
REQ1
I
PCI req signal.
R-D3.3V
A24
REQ2
I
PCI req signal.
R-D3.3V
C23
REQ3
I
PCI req signal.
R-D3.3V
E21
FRAME#_SIZI
I/O
PCI bus FRAME# signal/68K Transfer size bit 1. 
(along with Transfer size bit 0 to indicate the number byte to be 
transferred during a bus cycle M68K CPU bus.)
PCI_FRAM
A20
IRDY_PCAS
I/O
PCI bus IRDY# signal/68K address strobe signal.
PCI_IRDY
B20
CBE2#_FRA18
I/O
PCI bus CBE#[2]/Flash address bit 18.
FRA_18
D20
TRDY#_SIZ0
I/O
PCI bus TRDY# signal/68K Transfer size bit 0.
PCI_TRDY
B19
SEPR#_DSACK1
I/O
PCI bus SERR# signal/68K Data and Size acknowledge signal bit 1. PCI_SERR
C19
DVSEL_PCDS
I/O
PCI bus DEVSEL# signal/68K Data Strobe signal.
PCI_DVSL
D19
PAR_DSACK0
I/O
PCI bus PAR signal/68K Data and Size acknowledge signal bit 0.
PCI_PAR
E20
STOP#_PCRW
I/O
PCI bus STOP signal/Flash, 3.3V CMOS IF, 16mA output pad.
PCI_STOP
POD Interface
B12
POD_ITX
I
POD OOB TXI Channel.
R-D3.3V
C12
POD_WAIT
I
POD WAIT# signal to expand bus cycle.
POD_WAIT
D12
POD_CE1
O
Card enable.
POD_CEI
E12
POD_CTX
O
POD OOB TX Gapped Symbol clock.
R-D3.3V
A11
POD_DRX
O
POD OOB RX data.
R-D3.3V
B11
POD_CD1
I
Card Detect.
POD_CDI
C11
POD_IREQ
I
Ready/IRQ
POD_IREQ
D11
POD_CRX
O
POD OOB RX Gapped clock.
R-D3.3V
E11
POD_RESET
O
POD Card reset signal.
POD_RESET
A10
POD_QTX
I
POD OOB TX Q Channel.
R-D3.3V
B10
POD_VS1
I
Card voltage Sense.
POD_VS1
C10
POD_ETX
I
POD OOB TX enable.
R-D3.3V
D10
POD_CD2
I
Card Detect.
POD_CD2
E10
POD_CE2
O
Card enable.
POD_CE2
A9
POD_VPP_EN
O
Slot VPP enable.
R-D3.3V
B9
POD_OVERLOAD
I
Current overload detect.
R-D3.3V
C9
POD_VPP_EN#
O
Slot VPP enable.
R-D3.3V
D9
POD_VCC_EN#
O
Slot VCC enable.
R-D3.3V
E9
POD_VCC_EN
O
Slot VCC enable.
R-D3.3V
A8
POD_A9
O
POD Host interface address bit 9.
POD_A9
B8
POD_A8
O
POD Host interface address bit 8.
POD_A8
C8
POD_A7
I/O
POD Host interface address bit 7.
POD_A7
D8
POD_A6
I/O
POD Host interface address bit 6.
POD_A6
D7
POD_A5
I/O
POD Host interface address bit 5.
POD_A5
C7
POD_A4
O
POD Host interface address bit 4.
POD_A4
VDA Interface
AP13, AN13, AM13, 
AL13, AK13, AP14, 
AN14, AM14, AL14, 
AK14
VDA_R[9:0]
I
Video input, R channel. (no connected)
R-GND
AP15, AN15, AM15, 
AL15, AK15, AM16, 
AL16, AK16, AP17, 
AN17
VDA_B[9:0]
I
Video input, B channel. (no connected)
R-GND
AM17, AL17, AK17, 
AP18, AN18, AM18, 
AL18, AK18, AP19, 
AN19
VDA_G[9:0]
I
Video input, G channel. (no connected)
R-GND
AP16
VDA_CLK
I
Video input, Clock. (no connected)
R-GND
AM19
VDA_VS
I
Video input, Vertical sync. (no connected)
R-GND
AL19
VDA_HS
I
Video input, Horizontal sync. (no connected)
R-GND
AK19
VDA_DE
I
Video input, Data enable. (no connected)
R-GND
VDB Interface, EJTAG, IDE and POD2 share with VDB
AK20
VDB_DE
I/O
Video input/output: data enable;
IDE: IDE bus interrupt.
EJTAG: NOP
POD2: POD_CE2B#, the second POD Card enable.
VDB_DE
AL20
VDB_HS
I/O
Video input/output: Horizontal sync;
IDE: PDIAGCBLID, Passed diagnostics, cable assembly type identi-
fier.
EJTAG: TDI2, TDI EJTAG input of slave CPU.
POD2: POD_A_B5, the second POD host interface address bit 5.
VDB_HS
Pin No.
Pin Name
I/O
Pin Function
Sheet Name
LC-46X8E/S/RU
5 – 16
AM20
VDB_VS
I/O
Video input/output: Vertical sync;
IDE: DMAREQ, IDE bus DMA request.
EJTAG: NOP
POD2: POD_A_B4, the second POD host interface address bit 4.
VDB_VS
AN20
VDB_G0
I/O
Video input/output: Green channel bit 0;
IDE: IDE data bus bit 0.
EJTAG: TDO2, TDO EJTAG input of slave CPU CPU.
POD2: POD_A_B6, the second POD host interface address bit 6.
VDB_G0
AP20
VDB_G1
I/O
Video input/output: Green channel bit 1;
IDE: IDE data bus bit 1.
EJTAG: TMS2, TMS EJTAG input of slave CPU CPU.
POD2: POD_A_B7, the second POD host interface address bit 7.
VDB_G1
AK21
VDB_G2
I/O
Video input/output: Green channel bit 2;
IDE: IDE data bus bit 2.
EJTAG: TCK2, TCK EJTAG input of slave CPU CPU.
POD2: POD_A_B8, the second POD host interface address bit 8.
VDB_G2
AL21
VDB_G3
I/O
Video input/output: Green channel bit 3;
IDE: IDE data bus bit 3.
EJTAG: DCLK EJTAG output of both CPU CPUs.
POD2: POD_A_B8, the second POD host interface address bit 9.
VDB_G3
AM21
VDB_G4
I/O
Video input/output: Green channel bit 4;
IDE: IDE data bus bit 4.
EJTAG: TPC[0], output as EJTAG PC Trace bus, bit 0.
POD2: POD_CD2B#, the second POD interface card detect.
VDB_G4
AN21
VDB_G5
I/O
Video input/output: Green channel bit 5;
IDE: IDE data bus bit 5.
EJTAG: TPC[1], output as EJTAG PC Trace bus, bit 1.
POD2: POD_CD1B#, the second POD interface card detect.
VDB_G5
AP21
VDB_G6
I/O
Video input/output: Green channel bit 6;
IDE: IDE data bus bit 6.
EJTAG: TPC[2], output as EJTAG PC Trace bus, bit 2.
POD2: POD_RSTB, the second POD host interface reset.
VDB_G6
AK22
VDB_G7
I/O
Video input/output: Green channel bit 7;
IDE: IDE data bus bit 7.
EJTAG: TPC[3], output as EJTAG PC Trace bus, bit 3.
POD2: POD_A_B14, the second POD host interface address bit 14.
VDB_G7
AL22
VDB_G8
I/O
Video input/output: Green channel bit 8;
IDE: IDE data bus bit 8.
EJTAG: TPC[4], output as EJTAG PC Trace bus, bit 4.
POD2: POD2_TS2_D0, the second POD TS2 data[0].
VDB_G8
AM22
VDB_G9
I/O
Video input/output: Green channel bit 9;
IDE: IDE data bus bit 9.
EJTAG: TPC[5], output as EJTAG PC Trace bus, bit 5.
POD2: POD2_TS2_D2, the second POD TS2 data[1].
VDB_G9
AN22
VDB_B0
I/O
Video input/output: Blue channel bit 0;
IDE: IDE data bus bit 10.
EJTAG: TPC[6], output as EJTAG PC Trace bus, bit 6.
POD2: POD2_TS2_D2, the second POD TS2 data[2].
VDB_B0
AP22
VDB_B1
I/O
Video input/output: Blue channel bit 1;
IDE: IDE data bus bit 11.
EJTAG: TPC[7], output as EJTAG PC Trace bus, bit 7.
POD2: POD2_TS2_D3, the second POD TS2 data[3].
VDB_B1
AK23
VDB_B2
I/O
Video input/output: Blue channel bit 2;
IDE: IDE data bus bit 12.
EJTAG: PCST[0], output as EJTAG PC Trace bus, bit 0.
POD2: POD2_TS2_D4, the second POD TS2 data[4].
VDB_B2
AL23
VDB_B3
I/O
Video input/output: Blue channel bit 3;
IDE: IDE data bus bit 13.
EJTAG: PCST[1], output as EJTAG PC Trace bus, bit 1.
POD2: POD2_TS2_D5, the second POD TS2 data[5].
VDB_B3
AM23
VDB_B4
I/O
Video input/output: Blue channel bit 4;
IDE: IDE data bus bit 14.
EJTAG: PCST[2], output as EJTAG PC Trace bus, bit 2.
POD2: POD2_TS2_D6, the second POD TS2 data[6].
VDB_B4
AP23
VDB_CLK
I/O
Video input/output: Clock;
IDE: IDE data bus IO access complete.
EJTAG: NOP
POD2: POD_CE1B#, the second POD interface card enable.
VDB_CLK
Pin No.
Pin Name
I/O
Pin Function
Sheet Name
Page of 29
Display

Click on the first or last page to see other LC-46X8E service manuals if exist.

RANDOM: