Sharp LC-42XD1E (serv.man6) Service Manual ▷ View online
LC-42XD1E/RU
5 – 17
B11
GNDGENFSYN
—
Dedicated ground for nonaudio clock frequency synthe-
sizer
sizer
GNDF3
AA4
VDDAADAC
—
3.3 V power for audio DAC
VDDADCA
AA2
VSSAADAC
—
Ground for audio DAC command switches
GNDADAC
Y4
VDDASADAC
—
3.3 V power for audio DAC substrate
VDDADAC
AB2
VCCAADAC
—
3.3 V power for audio DAC command switches
VDDA
AB3
GNDAADAC
—
Ground for audio DAC
GNDADAC
AC2
VCCASADAC
—
3.3 V power for audio DAC command switches
substrate
substrate
VDDA
AD2
IREF
I
Audio DAC output reference current
AE2
VBGFIL
I
Audio DAC filtered output reference voltage
VBGFIL
AF4
LPCLKIN
I
Low power clock input (1.8 V tolerant)
CLOCK IN
AF5
LPCLKOSC
I/O
Low power clock oscillator (1.8 V tolerant)
CLOCK
A16
NO32XTAL1
I
Select for 32 kHz clock source
0: XTAL, 1: Internal divider
0: XTAL, 1: Internal divider
TCK
A13
CLK27MA
I
Selectable input clock to PLL or for x1 mode (5 V toler-
ant)
ant)
CLK27MHZ
A11
CLKSPEEDSEL
I
PLL speed select (5 V tolerant)
A12
AUXCLKOUT
O
Auxiliary clock for general use (5 V tolerant)
AF6
notRESET
I
System reset (1.8 V tolerant)
SYSRESET
AD14
notWDOGRSTOUT
O
Internal watchdog timer reset (5 V tolerant)
AE14
TDI
I
Boundary scan test data input (5 V tolerant)
TDI
AC14
TMS
I
Boundary scan test mode select (5 V tolerant)
TMS
AF16
TCK
I
Boundary scan test clock (5 V tolerant)
TCK
AF14
notTRST
I
Boundary scan test logic reset (5 V tolerant)
NOTTRST
AE13
TDO
O
Boundary scan test data output (5 V tolerant)
TDO
P1
DCUTRIGGERIN
I
External trigger input to DCU (5 V tolerant)
TRIGIN
P3
DCUTRIGGEROUT
O
Signal to trigger external debug circuitry (5 V tolerant)
TRIGOUT
C23
TSIN2LBYTECLK
I/O
Transport stream bit clock (5 V tolerant)
TS2CLK
C22
TSIN2LBYTECLKVALI
D
D
I/O
Transport stream bit clock valid edge (5 V tolerant)
TS2VAL
B23
TSIN2LERROR
I/O
Transport stream packet error (5 V tolerant)
D19
TSIN2LPACKETCLK
I/O
Transport stream packet strobe (5 V tolerant)
TS2STRT
B18, C18, D18, C19, C20,
D20, C21, D21
D20, C21, D21
TSIN2LDATA[7:0]
I/O
Transport stream data (5 V tolerant)
TS2D[7:0]
P23
TSIN1BYTECLK
I
Transport stream bit/byte clock (5 V tolerant)
FECLK
M24
TSIN1BYTECLKVALID
I
Transport stream bit/byte clock valid edge (5 V tolerant)
FEVALID
M26
TSIN1ERROR
I
Transport stream packet error (5 V tolerant)
FEERROR
N26
TSIN1PACKETCLK
I
Transport stream packet strobe (5 V tolerant)
FESTROUT
K26, J25, H24, J24, L26,
L25, L24, M23
L25, L24, M23
TSIN1DATA[7:0]
I
Transport stream data in (5 V tolerant)
FED[7:0]
L3
notEMIRAS or
notCI_IORD1
notCI_IORD1
O
Row address strobe for SDRAM
EMIRAS
K1
not_EMICAS or
not_CI_IOW1
not_CI_IOW1
O
Column address strobe for SDRAM
EMICAS
J1
notEMICSA
O
Peripheral chip select A
EMICSO
K3
notEMICSB
O
Peripheral chip select B
K2
notEMICSC
O
Peripheral chip select C
N4
notEMICSD
O
Peripheral chip select D
EMICS3
J2
notEMICSE
O
Peripheral chip select E
L2
notEMICSF
O
Peripheral chip select F
EMICS5
L1, N3
notEMIBE[1:0]
O
External device data bus byte enable. 1 bit per byte of
the data bus.
the data bus.
EMIBE1,
EMIRAS
EMIRAS
N1
notEMIOE or
not_CI_OE
not_CI_OE
O
External device output enable.
EMIOE
N2
notEMILBA or
notCI_Wea
notCI_Wea
O
Flash device load burst address.
EMILBA
P4
EMIWAITnotTREADY
I
External memory device target ready indicator (5 V tol-
erant)
erant)
CPUWAIT
P2
EMIRDnotWR
O
External read/write access indicator. Common to all
devices.
devices.
EMIRW
H3, H2, G2, H4, G4, E2,
E1, E3, H1, D1, D2, C2,
G3, C1, B1, A1
E1, E3, H1, D1, D2, C2,
G3, C1, B1, A1
EMIDATA[15:0]
I/O
External common data bus.
EMID[15-0]
Pin No.
Pin Name
I/O
Pin Function
NET NAME
LC-42XD1E/RU
5 – 18
D5, C5, D6, B3, A2, B2,
A3, B4, A4, C6, B5, A5,
D7, C7, B6, A6, B7, A7,
D9, C9, B9, A9, B10, C11
A3, B4, A4, C6, B5, A5,
D7, C7, B6, A6, B7, A7,
D9, C9, B9, A9, B10, C11
EMIADDR[25:2]
O
External common address bus
EMIA[23-2]
(D5,C5=NC)
(D5,C5=NC)
J3
notEMIREQGNT
O
Bus request/grant indicator
NC
K4
notEMIACKREQ
I
Bus grant/request indicator (5 V tolerant)
L4
EMIBOOTMODE0
I
External power-up port size indicator (5 V tolerant)
G1
EMISDRAMCLK
O
SDRAM clock
EMICLK
J4
EMIFLASHCLK
O
Peripheral clock
NC
W1, U4, U2, U1, R2, R1,
T2, T1
T2, T1
PIO0[7:0]
I/O
Parallel input/output pin or alternative function (5 V tol-
erant)
(U1:MUTE,R2:VIDEOOFF,R1:MDMRESET,T2:FERE-
SET,T1:CIRESET)
erant)
(U1:MUTE,R2:VIDEOOFF,R1:MDMRESET,T2:FERE-
SET,T1:CIRESET)
AB4, Y2, AA1, Y1, W3,
U3, W2, W4
U3, W2, W4
PIO1[7:0]
I/O
(W2:TVRX,W4:TVTX)
AF3, AD5, AE3, AE5, AF2,
Y3, AA3, AF1
Y3, AA3, AF1
PIO2[7:0]
I/O
(AF3:ASPECT,AD5:IRQ,AA3:GPIO1,AF1:GPIO0)
AE18, AE4, AC16, AC12,
AE6, AC11, AC5, AE12
AE6, AC11, AC5, AE12
PIO3[7:0]
I/O
(AE6:TVSCL,AC11:TVSDA,AC5:I2CSCL,AE12:I2CSDA
)
)
AE20, AD20, AF20, AE19,
AC17, AD18, AD17, AF19
AC17, AD18, AD17, AF19
PIO4[7:0]
I/O
(AE20:27MHzPWM,)
AC22, AF22, AD21, AC21,
AE21, AC18, AC20, AF21,
AE21, AC18, AC20, AF21,
PIO5[7:0]
I/O
(AD21:RXD,AC21:TXD,AF21:IR)
AF17
SCLK
O
Serial clock (5 V tolerant)
NC
AE17
PCMDATA1
O
PCM data out (5 V tolerant)
NC
AE16
PCMCLK
I/O
External PCM clock input or internal PCM clock output
(5 V tolerant)
(5 V tolerant)
NC
AF18
LRCLK
O
Left/right clock (5 V tolerant)
TL4027
AD16
SPDIF
O
Digital audio output (5 V tolerant)
SPDIF
AD26, AB25, AB24, AC25,
AE26, AB23, AE25, AF26,
AD25, AF25, AE24, AF24,
AF23, AE23
AE26, AB23, AE25, AF26,
AD25, AF25, AE24, AF24,
AF23, AE23
SMIADDR[13:0]
O
SDRAM address bus
SMIA[13-0]
U26, U25, R23, V26, V25,
T23, V24, V23, W26, W25,
Y25, Y26, Y23, AB26,
Y24, AC26
T23, V24, V23, W26, W25,
Y25, Y26, Y23, AB26,
Y24, AC26
SMIDATA[15:0]
I/O
SDRAM data bus
SMID[15-0]
T24
notSMICS0
O
SDRAM chip select for 1st SDRAM
SMICS
T25
notSMICS1
O
SDRAM chip select for 2nd 16 Mbit SDRAM
T26
notSMICAS
O
SDRAM column address strobe
SMICAS
R24
notSMIRAS
O
SDRAM row address strobe
SMIRAS
R25
notSMIWE
O
SDRAM write enable
SMIWE
P26
SMIMEMCLKIN
I
SDRAM memory clock input
R26
SMIMEMCLKOUT
O
SDRAM memory clock output
SMICLK
P24
SMIDATAML
O
SDRAM data bus lower byte enable
SMIDQML
P25
SMIDATAMU
O
SDRAM data bus upper byte enable
SMIDQMI
B15, A15, D16, C16, B16,
B17, C17, D17
B17, C17, D17
P1284DATA[7:0]
I/O
1284 AV data (5 V tolerant)
NC
C15
notP1284SELECTIN
I/O
1284 AV control signals (5 V tolerant)
NC
D15
notP1284INIT
I/O
NC
A14
notP1284FAULT
I/O
NC
B14
notP1284AUTOFD
I/O
NC
C14
P1284SELECT
I/O
NC
D14
P1284PERROR
I/O
NC
D13
P1284BUSY
I/O
NC
D12
notP1284ACK
I/O
NC
D11
notP1284STROBE
I/O
NC
T4, R4, T3, R3
INTERRUPT[3:0]
I/O
External interrupts (5 V tolerant)
MODEMIRQ, TL4003,
CIIRQ1, CIIRQ0
CIIRQ1, CIIRQ0
AE1
OUTPLEFT
O
Left channel, differential positive current output
LEFTP
AC1
OUTMLEFT
O
Left channel, differential negative current output
LEFTM
AD1
OUTPRIGHT
O
Right channel, differential positive current output
RIGHTP
AB1
OUTMRIGHT
O
Right channel, differential negative current output
RIGHTM
AF12
ROUT
O
Red output
R
AF11
GOUT
O
Green output
G
AF13
BOUT
O
Blue output
B
Pin No.
Pin Name
I/O
Pin Function
NET NAME
LC-42XD1E/RU
5 – 19
13. IC4201/4202: RH-iXB742WJZZQ
64Mb- SDRAM
14. IC4203: RH-iXB921WJZZQ
16Mbit Flash Memory
AF8
COUT
O
Chroma output
COUT
AF9
CVOUT
O
Composite video output
CVBS
AF10
YOUT
O
Luma output
YOUT
AD22
notHSYNC
I/O
Horizontal sync (5 V tolerant)
NC
AE22
EVENnotODD
I/O
Vertical sync (5 V tolerant)
TL4016
Pin No.
Pin Name
I/O
Pin Function
38
CLK
I
Active on the positive going edge to sample all inputs.
19
CS
I
Disables or enables device operation by masking or enabling all inputs except
CLK,CKE and DQM.
CLK,CKE and DQM.
37
CKE
I
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
22-26, 29-35
A0-A11
I
Row/column addresses are multiplexed on the same pins.
Row address: RA0-RA11, Column address: CA0-CA8
Row address: RA0-RA11, Column address: CA0-CA8
20, 21
BA0-BA1
I
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Selects bank for read/write during column address latch time.
18
RAS
I
Latches row address on the positive going edge of the CLK with RAS low.
Enables row access precharge.
Enables row access precharge.
17
CAS
I
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables column access.
16
WE
I
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Latches data in starting from CAS, WE active.
15, 39
DQM
I/O
Makes data output Hi-Z, tsHZ after the clock and masks the output. Blocks data
input when DQM active.
input when DQM active.
2, 4, 5, 7, 8, 10, 11, 13, 42,
44, 45, 47, 48, 50, 51, 53
44, 45, 47, 48, 50, 51, 53
DQ0-X15
I/O
Data input/output are mutiplexed on the same pins
(X16;DQ0-15)
(X16;DQ0-15)
1, 14, 27, 28, 41, 54
VDD/VSS
—
Power and ground for the input buffers and the core logic.
3, 6, 9, 12, 43, 46, 49, 52
VDDQ/VSSQ
—
Lsolated power supply and ground for the output buffers to provide improved
noise immunity.
noise immunity.
40
N.C/RFU
—
This pin is recommended to be left No Connection on the device.
Pin No.
Pin Name
I/O
Pin Function
1-10, 16-25, 48,13
A2-A22
I
22 Address Input.
29, 31, 33, 35, 38, 40, 42, 44 DQ0-DQ7
I/O
8 Data Input/Output.
30, 32, 34, 36, 39, 41, 43
DQ8-DQ14
I/O
Data Input/Output.
45
DQ15A-1
I/O
Data Input/Output or Address Input.
26
E
I
Chip Enable.
28
G
O
Output Enable
11
W
I
Write Enable.
12
RP
I
Reset/Block Temporary Unprotect.
15
RB
O
Read/Busy Output.
47
BYTE
I
Byte/Word Organization Select.
37
Vcc
—
Supply Voltage.
27, 46
Vss
—
Ground.
N.C.
—
Not Connected Internally.
Pin No.
Pin Name
I/O
Pin Function
NET NAME
LC-42XD1E/RU
5 – 20
15. IC4402: VHiLCX573FT-1Y
Latch 3-State output
16. IC4401: VHiTCLCX245-2Y
Interactive Balance Tranceiver
Pin No.
Pin Name
I/O
Pin Function
1
OE
I
Output Enable.
2
D0
I
Data Input D0.
3
D1
I
Data Input D1.
4
D2
I
Data Input D2.
5
D3
I
Data Input D3.
6
D4
I
Data Input D4.
7
D5
I
Data Input D5.
8
D6
I
Data Input D6.
9
D7
I
Data Input D7.
10
GND
—
Ground.
11
LE
I
Limited Enable.
12
Q7
O
Data Output Q7.
13
Q6
O
Data Output Q6.
14
Q5
O
Data Output Q5.
15
Q4
O
Data Output Q4.
16
Q3
O
Data Output Q3.
17
Q2
O
Data Output Q2.
18
Q1
O
Data Output Q1.
19
Q0
O
Data Output Q0.
20
VCC
—
Power Source.
Pin No.
Pin Name
I/O
Pin Function
1
DIR
I
Directory.
2
A1
I/O
A-Bus. Output/Input Terminal A1.
3
A2
I/O
A-Bus. Output/Input Terminal A2.
4
A3
I/O
A-Bus. Output/Input Terminal A3.
5
A4
I/O
A-Bus. Output/Input Terminal A4.
6
A5
I/O
A-Bus. Output/Input Terminal A5.
7
A6
I/O
A-Bus. Output/Input Terminal A6.
8
A7
I/O
A-Bus. Output/Input Terminal A7.
9
A8
I/O
A-Bus. Output/Input Terminal A8.
10
GND
—
Ground A9
11
B8
I/O
B-Bus Input/Output Terminal B8.
12
B7
I/O
B-Bus Input/Output Terminal B7.
13
B6
I/O
B-Bus Input/Output Terminal B6.
14
B5
I/O
B-Bus Input/Output Terminal B5
15
B4
I/O
B-Bus Input/Output Terminal B4
16
B3
I/O
B-Bus Input/Output Terminal B3
17
B2
I/O
B-Bus Input/Output Terminal B2
18
B1
I/O
B-Bus Input/Output Terminal B1
19
OE
I
Output enable.
20
VCC
—
Power Source.
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