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IC 3800: STANDBY CONTROLLER 
Part number: STM8S105K4T6CTR (ST MICRO) 
Sharp code: RH-IXD550WJZZY 

http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/CD00200092.pdf

 

 

 

 

Core. 

o  16 MHz advanced STM8 core with Harvard architecture and 3-stage pipeline. 

o  Extended instruction set. 

 

Memories. 

o  Medium-density Flash/EEPROM:  

ƒ  Program memory up to 32 Kbytes (data retention: 20 years at 55°C after 10k cycles). 

ƒ  Data memory up to 1 Kbytes true data EEPROM (endurance 300k cycles). 

o  RAM: Up to 2 Kbytes. 

 

Clock, reset and supply management. 

o  2.95 V to 5.5 V operating voltage. 

o  Flexible clock control, 4 master clock sources: 

ƒ  Low power crystal resonator oscillator. 

ƒ  External clock input. 

ƒ  Internal, user-trimmable 16 MHz RC. 

ƒ  Internal low power 128 kHz RC. 

 

Clock security system with clock monitor. 

 

Power management: 

o  Low power modes (wait, active-halt, halt).  

o  Switch-off peripheral clocks individually. 

 

Permanently active, low consumption power-on and 
power-down reset. 

 

Interrupt management 

o  Nested interrupt controller with 32 interrupts. 

o  Up to 37 external interrupt on 6 vectors. 

 

Timers. 

o  2x 16-bit general purpose timers, with 2+3 

CAPCOM channels (IC, OC or PWM). 

o  Advanced control timer: 16-bit, 4 CAPCOM 

channels, 3 complementary outputs, dead-
time insertion and flexible synchronization. 

o  8-bit basic timer with 8-bit prescaler. 

o  Auto wake-up timer. 

o  Window and independent watchdog timers. 

 

Communications interfaces. 

o  UART with clock output for synchronous 

operation, Smartcard, IrDA, LIN. 

o  SPI interface up to 8 Mbit/s. 

o  I2C interface up to 400 Kbit/s. 

 

Analog-to-digital converter (ADC). 

o  10-bit, ±1 LSB ADC with up to 10 

multiplexed channels, scan mode and analog 
watchdog. 

 

I/Os. 

o  Up to 38 I/Os on a 48-pin package including 

16 high sink outputs. 

o  Highly robust I/O design, immune against 

current injection 

 

Unique ID. 

o  96-bit unique key for each device. 

 
 
 
 
 
 

IC8401: 2Gbit NAND FLASH 
Part number: MT29F4G08ABADAWP:D (MICRON) 
Sharp code: RH-IXD552WJQZQ 

http://datasheet.elcodis.com/pdf2/69/78/697874/mt29f4g08abadawpd.pdf

 

 
Micron NAND Flash devices include an asynchronous data interface for high-performance I/O operations. These devices use a 
highly multiplexed 8-bit bus (I/Ox) to transfer commands, address, and data. There are five control signals used to implement the 
asynchronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals control hardware write protection and monitor 
device status (R/B#). 
This hardware interface creates a low pin-count device 
with a standard pinout that remains the same from one 
density to another, enabling future upgrades to higher 
densities with no board redesign. 
A target is the unit of memory accessed by a chip enable 
signal. A target contains one or more NAND Flash die. A 
NAND Flash die is the minimum unit that can 
independently execute commands and report status. A 
NAND Flash die, in the ONFI specification, is referred to 
as a logical unit (LUN). There is at least one NAND Flash 
die per chip enable signal. For further details, see Device 
and Array Organization. 
This device has an internal 4-bit ECC that can be enabled 
using the GET/SET features. 
 
These devices use NAND Flash electrical and command 
interfaces. Data, commands, and addresses are multiplexed onto the same pins and received by I/O control circuits. The 
commands received at the I/O control circuits are latched by a command register and are transferred to control logic circuits for 
generating internal signals to control device operations. The addresses are latched by an address register and sent to a row 
decoder to select a row address or to a column decoder to select a column address. Data is transferred to or from the NAND 
Flash memory array, byte by byte (x8) or word by word (x16), through a data register and a cache register. The NAND Flash 
memory array is programmed and read using page-based operations and is erased using block-based operations. During normal 
page operations, the data and cache registers act as a single register. During cache operations, the data and cache registers 
operate independently to increase data throughput. The status register reports the status of die operations. 
 
 
IC9501: Single Port 10/100 Fast Ethernet Transceiver 
Part number: KSZ8081RNDTR (MICREL) 
Sharp code: RH-IXD543WJZZY 

http://www.mouser.com/catalog/specsheets/KSZ8081RNDCA.pdf

 

 
The KSZ8081RND is a single-supply 10BaseT-100Base-TX Ethernet physical-layer transceiver for transmission and reception 
of data over standard CAT-5 unshielded twisted pair (UTP) cable. 
The KSZ8081 is a highly-integrated PHY solution. It reduces board cost and simplifies board layout by using on-chip 
termination resistors for the differential pairs and by integrating a low-noise regulator to supply the 1.2V core, and by offering 
1.8/2.5/3.3V digital I/O interface support. 
The KSZ8081RND offers the Reduced Media Independent Interface (RMII) for direct connection to RMII-compliant MACs in 
Ethernet processors and switches 
As the power-up default, the KSZ8081RND uses a 25MHz crystal to generate all required clocks, including the 50MHz RMII 
reference clock output for the MAC. 

 

Single-chip 10BaseT/100BaseTx IEEE 802.3 compliant Ethernet transceiver. 

 

RMII v1.2 Interface support with a 50MHz reference clock output to MAC. 

 

MDC/MDIO management interface for PHY register configuration. 

 

Programmable interrupt output. 

 

On-chip termination resistors for the differential pairs. 

 

Baseline wander correction. 

 

HP Auto MDI/MDI-X to detect and correct straight-through and crossover cable connections with disable and enable 
option. 

 

Auto-negotiation to automatically select the highest link-up speed (10/100Mbps) and duplex (half/full). 

 

Loopback modes for diagnostics. 

 

Single 3.3V power supply with VDD I/O options for 1.8V, 2.5V or 3.3V. 

 

Built-on 1.2V regulator for core.  

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
IC1106: Silicon Tuner (Analog & DVB-T/C/T2) 
Part number: Si2178-A20-GMR (SILICON LABS) 
Sharp code: RH-IXD518WJZZY 

http://www.silabs.com/Support%20Documents/TechnicalDocs/Si2178-short.pdf

 

 
The Si2178 integrates a PAL/SECAM/NTSC analog TV demodulator with a universal hybrid TV tuner supporting all worldwide 
digital and analog TV standards. The Si2178 requires no external balun and offers the lowest-cost BOM for a hybrid TV tuner 
with analog demodulator. By combining Silicon Labs' proven digital low-IF architecture with a 4th-generation RF front-end, the 
Si2178 maintains the highest performance that exceeds MOPLL-based tuners, including industry-leading 2nd-order distortion 
performance. 

Compared with competing silicon TV tuners, the Si2178 delivers an unprecedented level of front-end integration, resulting in the 
lowest number of external BOM components. No external tracking filters, wire-wound inductors, LNAs, SAW filters or 
inductive power supply filtering components are needed. The Si2178 offers low power consumption as well as an option for 
single or dual power supply operation. Also included is an internal power-on reset circuit, eliminating the need for external 
brownout protection components or additional pins in module applications.  

For next-generation digital TV broadcast standards, such as DVB-T2 and DVB-C2, that are sensitive to integrated phase noise, 
the Si2178 offers industry-leading phase noise performance. A software-selectable cable mode is also included which offers high 
return-loss performance. 

As with prior-generation Silicon Labs TV tuners, the Si2178 delivers superior picture quality and a higher number of received 
stations when compared to other silicon tuners and discrete MOPLL-based tuners. Both the tuner and analog demodulator 
incorporate worldwide field testing experience from three previous generations in high-volume production, to deliver the highest 
tolerance to real-world field reception conditions. The Si2178 also incorporates a harmonic-rejection mixer that delivers 
excellent immunity to Wi-Fi and LTE interference across the full RF input frequency range, with no need for external filtering 
components. 

 

Features: 

 

Worldwide hybrid TV tuner. 

o  Analog TV: NTSC, PAL/SECAM. 

o  Digital TV: ATSC/QAM, DVB-T2/T/C2/C, ISDB-T/C, DTMB. 

o  42–1002 MHz frequency range. 

 

Analog TV demodulator. 

o  Superior video SNR performance. 

o  Over modulation and ICPM tolerant. 

 

Industry-leading margin to A/74, NorDig, D-Book, C-Book, ARIB, EN55020, Open Cable™ specifications. 

 

Lowest BOM for a silicon hybrid TV tuner. 

o  No balum at RF input. 

o  No external SAW filters or wire-wound inductors. 

o  Integrated LNAs and complete tracking filters. 

 

Best-in-class real-world reception. 

o  Exceeds discrete MOPLL-based tuners. 

o  Industry-leading phase noise performance. 

o  High immunity to Wi-Fi and LTE interference. 

 

Low power consumption. 

o  3.3 V and 1.8 V power supplies. 

o  Single-supply option for 3.3 V-only operations. 

 

Integrated power-on reset circuit. 

 

Flexible output interface. 

o  Combined ALIF/DLIF output to SoC. 

o  Optional DLIF output to external demodulator.  

 

IC1102: DVB-T/C Demodulator. 
Part number: Si2165-D-GMR (SILICON LABS) 
Sharp code: RH-IXD519WJZZY

http://www.silabs.com/Support%20Documents/TechnicalDocs/Si2165-short.pdf

 

 
The Si2165 is a compact standalone DVB-T/C digital TV. The analog front-end consists of two ADCs with wide dynamic range 
(12-bit) to allow operation with standard IF (~36 MHz), Low-IF, or Zero-IF inputs. This enables the use of the Si2165 with any 
TV tuner, either metal can or silicon tuner based. 
The multi-standard demodulator supports all modes of DVB-T (EN 300 744), including hierarchical modes. The Si2165 also 
supports ITU J.83 annex A/C and DVB-C (EN 300 429), including a user-configurable 31-tap equalizer. In addition to DVB-T's 
legacy modes, the Si2165 also complies with DVB-H (EN 300 744 Annex F) specificities: 4K FFT, extended TPS, “native” and 
“in-depth” de-interleavers. The Si2165 is able to receive DVB-H programs in fixed receiver applications (without decoding the 
additional MPE FEC layer). 
An embedded 32-bit DSP controls device operation. Sophisticated on-chip algorithms ensure optimum reception even under 
difficult channel conditions, such as echoes outside the guard interval, pre-echoes, or strong impulse noise. For ease-of-use, DSP 
firmware is preloaded into ROM (device is immediately active at power-up). Nevertheless, there is a possibility of downloading 
additional patch code via the I2C interface (e.g., to adjust the demodulator to unexpected conditions or reception impairments). 
Thanks to proprietary features, the Si2165 supports ultra-fast channel scanning for VHF/UHF terrestrial and cable DTV 
channels. For supported tuners, the Quickscan algorithm for blindscan is running onto the embedded DSP (in order to limit the 
host CPU load) and is provided as a downloadable patch file. 
Serial or parallel master MPEG TS output modes are supported. Furthermore, a TS slave parallel mode is available via a GPIF 
port and provides a glueless interface to Silicon Labs' MCU devices with embedded USB interface. The user can optionally 
program a 32-PID hardware filter to reduce the output TS bit rate. 
An internal I2C pass-through logic switch acts as an I2C repeater. This provides a “quiet” I2C bus to the RF front end. 
A maximum of six general-purpose inputs/outputs are available; three GPIOs also feature 

Δ/Σ and interrupt output capabilities. 

Best-in-class demodulation performance is achieved while still maintaining very low-power operation. 
The Si2165 guarantees a low-cost system implementation due to its minimal BOM and very small package footprint. 
 
Features: 

 

DVB-T (ETSI EN 300 744) demodulator & FEC decoder. 

 

ITU J.83 Annex A/C and DVB-C (EN 300 429) compliant demodulator & FEC decoder. 

 

NorDig Unified 2.0, D-Book & C-Book 4.0 compliant.